From 2ca6872584e6cfa9c54e492288bb70cbc957d8e7 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 24 Jun 2019 16:24:03 +0000 Subject: [PATCH] AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1 Try to fail for scc, since I don't think that should ever be produced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364199 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../AMDGPU/AMDGPUInstructionSelector.cpp | 17 +- lib/Target/AMDGPU/SIRegisterInfo.cpp | 19 ++- .../GlobalISel/inst-select-implicit-def.mir | 160 +++++++++++++++--- 3 files changed, 160 insertions(+), 36 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 6484b7d6421..590fd25a965 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -232,12 +232,17 @@ bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const { MachineFunction *MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); const MachineOperand &MO = I.getOperand(0); - const TargetRegisterClass *RC = - TRI.getConstrainedRegClassForOperand(MO, MRI); - if (RC) - RBI.constrainGenericRegister(MO.getReg(), *RC, MRI); - I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); - return true; + + // FIXME: Interface for getConstrainedRegClassForOperand needs work. The + // regbank check here is to know why getConstrainedRegClassForOperand failed. + const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, MRI); + if ((!RC && !MRI.getRegBankOrNull(MO.getReg())) || + (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, MRI))) { + I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); + return true; + } + + return false; } bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const { diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp index 0caeb81225d..fe675b52f1d 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1688,10 +1688,23 @@ SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO, Size = PowerOf2Ceil(Size); switch (Size) { - case 1: - if (RB->getID() == AMDGPU::SCCRegBankID) + case 1: { + switch (RB->getID()) { + case AMDGPU::VGPRRegBankID: + return &AMDGPU::VGPR_32RegClass; + case AMDGPU::VCCRegBankID: + // TODO: Check wavesize + return &AMDGPU::SReg_64_XEXECRegClass; + case AMDGPU::SGPRRegBankID: return &AMDGPU::SReg_32_XM0RegClass; - break; + case AMDGPU::SCCRegBankID: + // This needs to return an allocatable class, so don't bother returning + // the dummy SCC class. + return &AMDGPU::SReg_32_XM0RegClass; + default: + llvm_unreachable("unknown register bank"); + } + } case 32: return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass : &AMDGPU::SReg_32_XM0RegClass; diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir index 6d76d6ffd6a..133d51297c2 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir @@ -1,63 +1,107 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefixes=GCN %s +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefixes=ERR %s +# G_IMPLICIT_DEF should probably never be produced for scc. Make sure there's no crash. +# ERR: remark: :0:0: cannot select: %0:scc(s1) = G_IMPLICIT_DEF (in function: implicit_def_s1_scc) +# ERR-NOT: remark + +--- + +name: implicit_def_s32_sgpr +legalized: true +regBankSelected: true + +body: | + bb.0: + ; GCN-LABEL: name: implicit_def_s32_sgpr + ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF + ; GCN: S_ENDPGM 0, implicit [[DEF]] + %0:sgpr(s32) = G_IMPLICIT_DEF + S_ENDPGM 0, implicit %0 +... --- -name: implicit_def_s32 +name: implicit_def_s32_vgpr legalized: true regBankSelected: true body: | bb.0: - liveins: $vgpr3_vgpr4 - ; GCN-LABEL: name: implicit_def_s32 - ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 + ; GCN-LABEL: name: implicit_def_s32_vgpr ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; GCN: FLAT_STORE_DWORD [[COPY]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr - %0:vgpr(p1) = COPY $vgpr3_vgpr4 - %1:vgpr(s32) = G_IMPLICIT_DEF - G_STORE %1, %0 :: (store 4, addrspace 1) + ; GCN: S_ENDPGM 0, implicit [[DEF]] + %0:vgpr(s32) = G_IMPLICIT_DEF + S_ENDPGM 0, implicit %0 ... + --- -name: implicit_def_s64 +name: implicit_def_s64_sgpr legalized: true regBankSelected: true body: | bb.0: - liveins: $vgpr3_vgpr4 - ; GCN-LABEL: name: implicit_def_s64 - ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 - ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; GCN: FLAT_STORE_DWORDX2 [[COPY]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr - %0:vgpr(p1) = COPY $vgpr3_vgpr4 - %1:vgpr(s64) = G_IMPLICIT_DEF - G_STORE %1, %0 :: (store 8, addrspace 1) + ; GCN-LABEL: name: implicit_def_s64_sgpr + ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GCN: S_ENDPGM 0, implicit [[DEF]] + %0:sgpr(s64) = G_IMPLICIT_DEF + S_ENDPGM 0, implicit %0 +... + --- +name: implicit_def_s64_vgpr +legalized: true +regBankSelected: true + +body: | + bb.0: + ; GCN-LABEL: name: implicit_def_s64_vgpr + ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; GCN: S_ENDPGM 0, implicit [[DEF]] + %0:vgpr(s64) = G_IMPLICIT_DEF + S_ENDPGM 0, implicit %0 +... + --- +name: implicit_def_p0_sgpr +legalized: true +regBankSelected: true -name: implicit_def_p0 +body: | + bb.0: + ; GCN-LABEL: name: implicit_def_p0_sgpr + ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GCN: S_ENDPGM 0, implicit [[DEF]] + %0:sgpr(p0) = G_IMPLICIT_DEF + S_ENDPGM 0, implicit %0 +... + +--- +name: implicit_def_p0_vgpr legalized: true regBankSelected: true body: | bb.0: + ; GCN-LABEL: name: implicit_def_p0_vgpr + ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; GCN: S_ENDPGM 0, implicit [[DEF]] %0:vgpr(p0) = G_IMPLICIT_DEF - %1:vgpr(s32) = G_CONSTANT i32 4 - G_STORE %1, %0 :: (store 4) + S_ENDPGM 0, implicit %0 ... --- -name: implicit_def_p1 +name: implicit_def_p1_vgpr legalized: true regBankSelected: true body: | bb.0: - ; GCN-LABEL: name: implicit_def_p1 + ; GCN-LABEL: name: implicit_def_p1_vgpr ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr @@ -65,15 +109,16 @@ body: | %1:vgpr(s32) = G_CONSTANT i32 4 G_STORE %1, %0 :: (store 4, addrspace 1) ... + --- -name: implicit_def_p3 +name: implicit_def_p3_vgpr legalized: true regBankSelected: true body: | bb.0: - ; GCN-LABEL: name: implicit_def_p3 + ; GCN-LABEL: name: implicit_def_p3_vgpr ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr @@ -81,15 +126,16 @@ body: | %1:vgpr(s32) = G_CONSTANT i32 4 G_STORE %1, %0 :: (store 4, addrspace 1) ... + --- -name: implicit_def_p4 +name: implicit_def_p4_vgpr legalized: true regBankSelected: true body: | bb.0: - ; GCN-LABEL: name: implicit_def_p4 + ; GCN-LABEL: name: implicit_def_p4_vgpr ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr @@ -97,3 +143,63 @@ body: | %1:vgpr(s32) = G_CONSTANT i32 4 G_STORE %1, %0 :: (store 4, addrspace 1) ... + +--- + +name: implicit_def_s1_vgpr +legalized: true +regBankSelected: true + +body: | + bb.0: + ; GCN-LABEL: name: implicit_def_s1_vgpr + ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GCN: S_ENDPGM 0, implicit [[DEF]] + %0:vgpr(s1) = G_IMPLICIT_DEF + S_ENDPGM 0, implicit %0 +... + +--- + +name: implicit_def_s1_sgpr +legalized: true +regBankSelected: true + +body: | + bb.0: + ; GCN-LABEL: name: implicit_def_s1_sgpr + ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF + ; GCN: S_ENDPGM 0, implicit [[DEF]] + %0:sgpr(s1) = G_IMPLICIT_DEF + S_ENDPGM 0, implicit %0 +... + +--- + +name: implicit_def_s1_scc +legalized: true +regBankSelected: true + +body: | + bb.0: + ; GCN-LABEL: name: implicit_def_s1_scc + ; GCN: [[DEF:%[0-9]+]]:scc(s1) = G_IMPLICIT_DEF + ; GCN: S_ENDPGM 0, implicit [[DEF]](s1) + %0:scc(s1) = G_IMPLICIT_DEF + S_ENDPGM 0, implicit %0 +... + +--- + +name: implicit_def_s1_vcc +legalized: true +regBankSelected: true + +body: | + bb.0: + ; GCN-LABEL: name: implicit_def_s1_vcc + ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GCN: S_ENDPGM 0, implicit [[DEF]] + %0:vcc(s1) = G_IMPLICIT_DEF + S_ENDPGM 0, implicit %0 +... -- 2.40.0