From 2c5f2079745449d0b46c5261ee771c4605301b7b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 13 Jul 2018 22:41:50 +0000 Subject: [PATCH] [X86][SLH] Add VEX and EVEX conversion instructions to isDataInvariantLoad -Drop the intrinsic versions of conversion instructions. These should be handled when we do vectors. They shouldn't show up in scalar code. -Add the float<->double conversions which were missing. -Add the AVX512 and AVX version of the conversion instructions including the unsigned integer conversions unique to AVX512 Differential Revision: https://reviews.llvm.org/D49313 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337066 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../X86/X86SpeculativeLoadHardening.cpp | 32 +++++++++++-------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/lib/Target/X86/X86SpeculativeLoadHardening.cpp index a99fa203fa4..9f5f36b3458 100644 --- a/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -938,19 +938,25 @@ static bool isDataInvariantLoad(MachineInstr &MI) { case X86::SHRX64rm: // Conversions are believed to be constant time and don't set flags. - // FIXME: Add AVX versions. - case X86::CVTSD2SI64rm_Int: - case X86::CVTSD2SIrm_Int: - case X86::CVTSS2SI64rm_Int: - case X86::CVTSS2SIrm_Int: - case X86::CVTTSD2SI64rm: - case X86::CVTTSD2SI64rm_Int: - case X86::CVTTSD2SIrm: - case X86::CVTTSD2SIrm_Int: - case X86::CVTTSS2SI64rm: - case X86::CVTTSS2SI64rm_Int: - case X86::CVTTSS2SIrm: - case X86::CVTTSS2SIrm_Int: + case X86::CVTTSD2SI64rm: case X86::VCVTTSD2SI64rm: case X86::VCVTTSD2SI64Zrm: + case X86::CVTTSD2SIrm: case X86::VCVTTSD2SIrm: case X86::VCVTTSD2SIZrm: + case X86::CVTTSS2SI64rm: case X86::VCVTTSS2SI64rm: case X86::VCVTTSS2SI64Zrm: + case X86::CVTTSS2SIrm: case X86::VCVTTSS2SIrm: case X86::VCVTTSS2SIZrm: + case X86::CVTSI2SDrm: case X86::VCVTSI2SDrm: case X86::VCVTSI2SDZrm: + case X86::CVTSI2SSrm: case X86::VCVTSI2SSrm: case X86::VCVTSI2SSZrm: + case X86::CVTSI642SDrm: case X86::VCVTSI642SDrm: case X86::VCVTSI642SDZrm: + case X86::CVTSI642SSrm: case X86::VCVTSI642SSrm: case X86::VCVTSI642SSZrm: + case X86::CVTSS2SDrm: case X86::VCVTSS2SDrm: case X86::VCVTSS2SDZrm: + case X86::CVTSD2SSrm: case X86::VCVTSD2SSrm: case X86::VCVTSD2SSZrm: + // AVX512 added unsigned integer conversions. + case X86::VCVTTSD2USI64Zrm: + case X86::VCVTTSD2USIZrm: + case X86::VCVTTSS2USI64Zrm: + case X86::VCVTTSS2USIZrm: + case X86::VCVTUSI2SDZrm: + case X86::VCVTUSI642SDZrm: + case X86::VCVTUSI2SSZrm: + case X86::VCVTUSI642SSZrm: // Loads to register don't set flags. case X86::MOV8rm: -- 2.50.1