From 2ab66137f5f1ff9ab3fe8c2ece35574c4d0be359 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 1 Jul 2019 13:30:12 +0000 Subject: [PATCH] AMDGPU/GlobalISel: RegBankSelect for WWM/WQM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364763 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 ++ .../GlobalISel/regbankselect-amdgcn.wqm.mir | 31 +++++++++++++++++++ .../GlobalISel/regbankselect-amdgcn.wwm.mir | 31 +++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir diff --git a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 1dec867516c..7641469aa84 100644 --- a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -1506,6 +1506,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case Intrinsic::amdgcn_sdot8: case Intrinsic::amdgcn_udot8: case Intrinsic::amdgcn_fdiv_fast: + case Intrinsic::amdgcn_wwm: + case Intrinsic::amdgcn_wqm: return getDefaultMappingVOP(MI); case Intrinsic::amdgcn_ds_permute: case Intrinsic::amdgcn_ds_bpermute: diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir new file mode 100644 index 00000000000..e0e15e21ac8 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s + +--- +name: wqm_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: wqm_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), [[COPY]](s32) + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), %0 +... + +--- +name: wqm_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: wqm_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), [[COPY]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), %0 +... diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir new file mode 100644 index 00000000000..4147a78da36 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s + +--- +name: wwm_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: wwm_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), [[COPY]](s32) + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), %0 +... + +--- +name: wwm_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: wwm_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), [[COPY]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), %0 +... -- 2.40.0