From 2a53f0ee9e30765c457621c3578e12424aa84d0a Mon Sep 17 00:00:00 2001
From: Mikael Holmen <mikael.holmen@ericsson.com>
Date: Wed, 4 Oct 2017 07:42:45 +0000
Subject: [PATCH] Recommit [UnreachableBlockElim] Use COPY if PHI input is
 undef

This time invoking llc with "-march=x86-64" in the testcase, so we don't assume
the default target is x86.

Summary:
If we have

    %vreg0<def> = PHI %vreg2<undef>, <BB#0>, %vreg3, <BB#2>; GR32:%vreg0,%vreg2,%vreg3
    %vreg3<def,tied1> = ADD32ri8 %vreg0<kill,tied0>, 1, %EFLAGS<imp-def>; GR32:%vreg3,%vreg0

then we can't just change %vreg0 into %vreg3, since %vreg2 is actually
undef. We would have to also copy the undef flag to be able to change the
register.

Instead we deal with this case like other cases where we can't just
replace the register: we insert a COPY. The code creating the COPY already
copied all flags from the PHI input, so the undef flag will be transferred
as it should.

Reviewers: kparzysz

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38235

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314882 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/UnreachableBlockElim.cpp          |  5 ++-
 .../MIR/X86/unreachable-mbb-undef-phi.mir     | 38 +++++++++++++++++++
 2 files changed, 41 insertions(+), 2 deletions(-)
 create mode 100644 test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir

diff --git a/lib/CodeGen/UnreachableBlockElim.cpp b/lib/CodeGen/UnreachableBlockElim.cpp
index 407fd9b162e..bdd25f29aea 100644
--- a/lib/CodeGen/UnreachableBlockElim.cpp
+++ b/lib/CodeGen/UnreachableBlockElim.cpp
@@ -207,11 +207,12 @@ bool UnreachableMachineBlockElim::runOnMachineFunction(MachineFunction &F) {
           MachineRegisterInfo &MRI = F.getRegInfo();
           unsigned InputSub = Input.getSubReg();
           if (InputSub == 0 &&
-              MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg))) {
+              MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) &&
+              !Input.isUndef()) {
             MRI.replaceRegWith(OutputReg, InputReg);
           } else {
             // The input register to the PHI has a subregister or it can't be
-            // constrained to the proper register class:
+            // constrained to the proper register class or it is undef:
             // insert a COPY instead of simply replacing the output
             // with the input.
             const TargetInstrInfo *TII = F.getSubtarget().getInstrInfo();
diff --git a/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir b/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir
new file mode 100644
index 00000000000..d1d7e9d8ad5
--- /dev/null
+++ b/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir
@@ -0,0 +1,38 @@
+# RUN: llc -march=x86-64 %s -o - -run-pass=processimpdefs -run-pass=unreachable-mbb-elimination | FileCheck %s
+---
+name:            f
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gr32, preferred-register: '' }
+  - { id: 1, class: gr32, preferred-register: '' }
+  - { id: 2, class: gr32, preferred-register: '' }
+body:             |
+  bb.0:
+    %0 = IMPLICIT_DEF
+    JMP_1 %bb.1
+
+  bb.1:
+    %1 = PHI %0, %bb.0, %2, %bb.2
+    %2 = ADD32ri8 killed %1, 1, implicit-def %eflags
+    JMP_1 %bb.3
+
+  bb.2:
+    JMP_1 %bb.1
+
+  bb.3:
+...
+
+# bb2 above is dead and should be removed and the PHI should be replaced with a
+# COPY from an undef value since the bb0 value in the PHI is undef.
+
+# CHECK:  bb.0:
+# CHECK:    successors: %bb.1
+# CHECK:    JMP_1 %bb.1
+
+# CHECK:  bb.1:
+# CHECK:    successors: %bb.2
+# CHECK:    [[TMP1:%[0-9]+]] = COPY undef %{{[0-9]+}}
+# CHECK:    %{{[0-9]+}} = ADD32ri8 killed [[TMP1]], 1
+# CHECK:    JMP_1 %bb.2
+
+# CHECK:  bb.2:
-- 
2.40.0