From 27abbacf6615417d789e64ca04664c1f0f584868 Mon Sep 17 00:00:00 2001
From: Diana Picus <diana.picus@linaro.org>
Date: Fri, 24 Feb 2017 14:01:27 +0000
Subject: [PATCH] [ARM] GlobalISel: Select G_STORE

Same as selecting G_LOAD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296122 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstructionSelector.cpp     | 36 +++++++------
 .../ARM/GlobalISel/arm-instruction-select.mir | 50 +++++++++++++++++++
 2 files changed, 70 insertions(+), 16 deletions(-)

diff --git a/lib/Target/ARM/ARMInstructionSelector.cpp b/lib/Target/ARM/ARMInstructionSelector.cpp
index 84d9ac55361..c7ed3c3d6e3 100644
--- a/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -189,36 +189,39 @@ static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) {
   return Opc;
 }
 
-/// Select the opcode for simple loads. For types smaller than 32 bits, the
-/// value will be zero extended. Returns G_LOAD if it doesn't know how to select
-/// an opcode.
-static unsigned selectLoadOpCode(unsigned RegBank, unsigned Size) {
+/// Select the opcode for simple loads and stores. For types smaller than 32
+/// bits, the value will be zero extended. Returns the original opcode if it
+/// doesn't know how to select a better one.
+static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
+                                      unsigned Size) {
+  bool isStore = Opc == TargetOpcode::G_STORE;
+
   if (RegBank == ARM::GPRRegBankID) {
     switch (Size) {
     case 1:
     case 8:
-      return ARM::LDRBi12;
+      return isStore ? ARM::STRBi12 : ARM::LDRBi12;
     case 16:
-      return ARM::LDRH;
+      return isStore ? ARM::STRH : ARM::LDRH;
     case 32:
-      return ARM::LDRi12;
+      return isStore ? ARM::STRi12 : ARM::LDRi12;
     default:
-      return TargetOpcode::G_LOAD;
+      return Opc;
     }
   }
 
   if (RegBank == ARM::FPRRegBankID) {
     switch (Size) {
     case 32:
-      return ARM::VLDRS;
+      return isStore ? ARM::VSTRS : ARM::VLDRS;
     case 64:
-      return ARM::VLDRD;
+      return isStore ? ARM::VSTRD : ARM::VLDRD;
     default:
-      return TargetOpcode::G_LOAD;
+      return Opc;
     }
   }
 
-  return TargetOpcode::G_LOAD;
+  return Opc;
 }
 
 bool ARMInstructionSelector::select(MachineInstr &I) const {
@@ -309,6 +312,7 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
     I.setDesc(TII.get(ARM::ADDri));
     MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
     break;
+  case G_STORE:
   case G_LOAD: {
     const auto &MemOp = **I.memoperands_begin();
     if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
@@ -323,15 +327,15 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
     const auto ValSize = ValTy.getSizeInBits();
 
     assert((ValSize != 64 || TII.getSubtarget().hasVFP2()) &&
-           "Don't know how to load 64-bit value without VFP");
+           "Don't know how to load/store 64-bit value without VFP");
 
-    const auto NewOpc = selectLoadOpCode(RegBank, ValSize);
-    if (NewOpc == G_LOAD)
+    const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
+    if (NewOpc == G_LOAD || NewOpc == G_STORE)
       return false;
 
     I.setDesc(TII.get(NewOpc));
 
-    if (NewOpc == ARM::LDRH)
+    if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
       // LDRH has a funny addressing mode (there's already a FIXME for it).
       MIB.addReg(0);
     MIB.addImm(0).add(predOps(ARMCC::AL));
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index 25c5efd6a61..24b95647e95 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -16,6 +16,8 @@
   define void @test_load_f32() #0 { ret void }
   define void @test_load_f64() #0 { ret void }
 
+  define void @test_stores() #0 { ret void }
+
   define void @test_soft_fp_double() #0 { ret void }
 
   attributes #0 = { "target-features"="+vfp2,-neonfp" }
@@ -387,6 +389,54 @@ body:             |
     ; CHECK: BX_RET 14, _, implicit %d0
 ...
 ---
+name:            test_stores
+# CHECK-LABEL: name: test_stores
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: fprb }
+  - { id: 5, class: fprb }
+# CHECK: id: [[P:[0-9]+]], class: gpr
+# CHECK: id: [[I8:[0-9]+]], class: gpr
+# CHECK: id: [[I16:[0-9]+]], class: gpr
+# CHECK: id: [[I32:[0-9]+]], class: gpr
+# CHECK: id: [[F32:[0-9]+]], class: spr
+# CHECK: id: [[F64:[0-9]+]], class: dpr
+body:             |
+  bb.0:
+    liveins: %r0, %r1, %r2, %r3
+
+    %0(p0) = COPY %r0
+    %1(s8) = COPY %r3
+    %2(s16) = COPY %r2
+    %3(s32) = COPY %r1
+    %4(s32) = COPY %s0
+    %5(s64) = COPY %d2
+
+    G_STORE %1(s8), %0(p0) :: (store 1)
+    ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, _
+
+    G_STORE %2(s16), %0(p0) :: (store 2)
+    ; CHECK: STRH %[[I16]], %[[P]], _, 0, 14, _
+
+    G_STORE %3(s32), %0(p0) :: (store 4)
+    ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, _
+
+    G_STORE %4(s32), %0(p0) :: (store 4)
+    ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, _
+
+    G_STORE %5(s64), %0(p0) :: (store 8)
+    ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, _
+
+    BX_RET 14, _
+...
+---
 name:            test_soft_fp_double
 # CHECK-LABEL: name: test_soft_fp_double
 legalized:       true
-- 
2.50.1