From 271f77cd2f7a6d1cebe74aff72e02d56e36986ce Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Thu, 6 Jun 2019 09:22:37 +0000 Subject: [PATCH] [MIPS GlobalISel] Select fabs Select G_FABS for MIPS32. Differential Revision: https://reviews.llvm.org/D62903 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362690 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsInstructionSelector.cpp | 10 +++ lib/Target/Mips/MipsLegalizerInfo.cpp | 2 +- lib/Target/Mips/MipsRegisterBankInfo.cpp | 3 +- .../GlobalISel/instruction-select/fabs.mir | 65 +++++++++++++++++++ .../Mips/GlobalISel/legalizer/fabs.mir | 61 +++++++++++++++++ test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll | 27 ++++++++ .../Mips/GlobalISel/regbankselect/fabs.mir | 63 ++++++++++++++++++ 7 files changed, 229 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir create mode 100644 test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir create mode 100644 test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll create mode 100644 test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir diff --git a/lib/Target/Mips/MipsInstructionSelector.cpp b/lib/Target/Mips/MipsInstructionSelector.cpp index 8fddcca4cfe..ea9b2e51557 100644 --- a/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/lib/Target/Mips/MipsInstructionSelector.cpp @@ -357,6 +357,16 @@ bool MipsInstructionSelector::select(MachineInstr &I, I.eraseFromParent(); return true; } + case G_FABS: { + unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); + unsigned FABSOpcode = + Size == 32 ? Mips::FABS_S + : STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32; + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode)) + .add(I.getOperand(0)) + .add(I.getOperand(1)); + break; + } case G_GLOBAL_VALUE: { const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal(); if (MF.getTarget().isPositionIndependent()) { diff --git a/lib/Target/Mips/MipsLegalizerInfo.cpp b/lib/Target/Mips/MipsLegalizerInfo.cpp index 146ee754183..9161a0fb38b 100644 --- a/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -94,7 +94,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { getActionDefinitionsBuilder(G_FCONSTANT) .legalFor({s32, s64}); - getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) + getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS}) .legalFor({s32, s64}); getActionDefinitionsBuilder(G_FCMP) diff --git a/lib/Target/Mips/MipsRegisterBankInfo.cpp b/lib/Target/Mips/MipsRegisterBankInfo.cpp index 6a4ffe16a35..3ac81f74c62 100644 --- a/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -133,7 +133,8 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_FADD: case G_FSUB: case G_FMUL: - case G_FDIV: { + case G_FDIV: + case G_FABS: { unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); assert((Size == 32 || Size == 64) && "Unsupported floating point size"); OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx] diff --git a/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir b/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir new file mode 100644 index 00000000000..9f820fd4d7b --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir @@ -0,0 +1,65 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32 +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64 +--- | + + define void @fabs_f32() {entry: ret void} + define void @fabs_f64() {entry: ret void} + +... +--- +name: fabs_f32 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12 + + ; FP32-LABEL: name: fabs_f32 + ; FP32: liveins: $f12 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[FABS_S:%[0-9]+]]:fgr32 = FABS_S [[COPY]] + ; FP32: $f0 = COPY [[FABS_S]] + ; FP32: RetRA implicit $f0 + ; FP64-LABEL: name: fabs_f32 + ; FP64: liveins: $f12 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[FABS_S:%[0-9]+]]:fgr32 = FABS_S [[COPY]] + ; FP64: $f0 = COPY [[FABS_S]] + ; FP64: RetRA implicit $f0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = G_FABS %0 + $f0 = COPY %1(s32) + RetRA implicit $f0 + +... +--- +name: fabs_f64 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6 + + ; FP32-LABEL: name: fabs_f64 + ; FP32: liveins: $d6 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[FABS_D32_:%[0-9]+]]:afgr64 = FABS_D32 [[COPY]] + ; FP32: $d0 = COPY [[FABS_D32_]] + ; FP32: RetRA implicit $d0 + ; FP64-LABEL: name: fabs_f64 + ; FP64: liveins: $d6 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[FABS_D64_:%[0-9]+]]:fgr64 = FABS_D64 [[COPY]] + ; FP64: $d0 = COPY [[FABS_D64_]] + ; FP64: RetRA implicit $d0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = G_FABS %0 + $d0 = COPY %1(s64) + RetRA implicit $d0 + +... diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir b/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir new file mode 100644 index 00000000000..ffed3b23656 --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir @@ -0,0 +1,61 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32 +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64 +--- | + + define void @fabs_f32() {entry: ret void} + define void @fabs_f64() {entry: ret void} + +... +--- +name: fabs_f32 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12 + + ; FP32-LABEL: name: fabs_f32 + ; FP32: liveins: $f12 + ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 + ; FP32: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]] + ; FP32: $f0 = COPY [[FABS]](s32) + ; FP32: RetRA implicit $f0 + ; FP64-LABEL: name: fabs_f32 + ; FP64: liveins: $f12 + ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 + ; FP64: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]] + ; FP64: $f0 = COPY [[FABS]](s32) + ; FP64: RetRA implicit $f0 + %0:_(s32) = COPY $f12 + %1:_(s32) = G_FABS %0 + $f0 = COPY %1(s32) + RetRA implicit $f0 + +... +--- +name: fabs_f64 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6 + + ; FP32-LABEL: name: fabs_f64 + ; FP32: liveins: $d6 + ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 + ; FP32: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]] + ; FP32: $d0 = COPY [[FABS]](s64) + ; FP32: RetRA implicit $d0 + ; FP64-LABEL: name: fabs_f64 + ; FP64: liveins: $d6 + ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 + ; FP64: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]] + ; FP64: $d0 = COPY [[FABS]](s64) + ; FP64: RetRA implicit $d0 + %0:_(s64) = COPY $d6 + %1:_(s64) = G_FABS %0 + $d0 = COPY %1(s64) + RetRA implicit $d0 + +... diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll new file mode 100644 index 00000000000..e674248a310 --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32 +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64 + +declare float @llvm.fabs.f32(float) +define float @fabs_f32(float %a) { +; MIPS32-LABEL: fabs_f32: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: abs.s $f0, $f12 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %0 = call float @llvm.fabs.f32(float %a) + ret float %0 +} + +declare double @llvm.fabs.f64(double) +define double @fabs_f64(double %a) { +; MIPS32-LABEL: fabs_f64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: abs.d $f0, $f12 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %0 = call double @llvm.fabs.f64(double %a) + ret double %0 +} diff --git a/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir b/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir new file mode 100644 index 00000000000..2db4ca7207d --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir @@ -0,0 +1,63 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32 +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64 +--- | + + define void @fabs_f32() {entry: ret void} + define void @fabs_f64() {entry: ret void} + +... +--- +name: fabs_f32 +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12 + + ; FP32-LABEL: name: fabs_f32 + ; FP32: liveins: $f12 + ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12 + ; FP32: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]] + ; FP32: $f0 = COPY [[FABS]](s32) + ; FP32: RetRA implicit $f0 + ; FP64-LABEL: name: fabs_f32 + ; FP64: liveins: $f12 + ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12 + ; FP64: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]] + ; FP64: $f0 = COPY [[FABS]](s32) + ; FP64: RetRA implicit $f0 + %0:_(s32) = COPY $f12 + %1:_(s32) = G_FABS %0 + $f0 = COPY %1(s32) + RetRA implicit $f0 + +... +--- +name: fabs_f64 +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6 + + ; FP32-LABEL: name: fabs_f64 + ; FP32: liveins: $d6 + ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6 + ; FP32: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]] + ; FP32: $d0 = COPY [[FABS]](s64) + ; FP32: RetRA implicit $d0 + ; FP64-LABEL: name: fabs_f64 + ; FP64: liveins: $d6 + ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6 + ; FP64: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]] + ; FP64: $d0 = COPY [[FABS]](s64) + ; FP64: RetRA implicit $d0 + %0:_(s64) = COPY $d6 + %1:_(s64) = G_FABS %0 + $d0 = COPY %1(s64) + RetRA implicit $d0 + +... -- 2.50.1