From 24f705031bf6edd2446e8516ac58df7fcb7637af Mon Sep 17 00:00:00 2001 From: Hiroshi Inoue Date: Tue, 31 Jul 2018 05:10:36 +0000 Subject: [PATCH] [InstSimplify] tests for D48828, D49981: fold extraction from std::pair Updated unit tests for D48828 and D49981. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338350 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/Transforms/InstSimplify/AndOrXor.ll | 68 ++++++++++++++++++++---- test/Transforms/InstSimplify/shift.ll | 52 ++++++++++++++---- 2 files changed, 100 insertions(+), 20 deletions(-) diff --git a/test/Transforms/InstSimplify/AndOrXor.ll b/test/Transforms/InstSimplify/AndOrXor.ll index 251b4dea63b..b0fa1cfb8da 100644 --- a/test/Transforms/InstSimplify/AndOrXor.ll +++ b/test/Transforms/InstSimplify/AndOrXor.ll @@ -999,7 +999,7 @@ define i64 @shl_or_and2(i32 %a, i1 %b) { ret i64 %tmp5 } -define i32 @shl_or_and3(i32 %a, i32 %b) { +define i64 @shl_or_and3(i32 %a, i32 %b) { ; concatinate two 32-bit integers and extract lower 32-bit ; CHECK-LABEL: @shl_or_and3( ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 @@ -1007,16 +1007,14 @@ define i32 @shl_or_and3(i32 %a, i32 %b) { ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967295 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -; CHECK-NEXT: ret i32 [[TMP6]] +; CHECK-NEXT: ret i64 [[TMP5]] ; %tmp1 = zext i32 %a to i64 %tmp2 = zext i32 %b to i64 %tmp3 = shl nuw i64 %tmp1, 32 %tmp4 = or i64 %tmp2, %tmp3 %tmp5 = and i64 %tmp4, 4294967295 - %tmp6 = trunc i64 %tmp5 to i32 - ret i32 %tmp6 + ret i64 %tmp5 } define i32 @shl_or_and4(i16 %a, i16 %b) { @@ -1037,23 +1035,21 @@ define i32 @shl_or_and4(i16 %a, i16 %b) { ret i32 %tmp5 } -define i64 @shl_or_and5(i64 %a, i1 %b) { +define i128 @shl_or_and5(i64 %a, i1 %b) { ; CHECK-LABEL: @shl_or_and5( ; CHECK-NEXT: [[TMP1:%.*]] = zext i64 [[A:%.*]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i128 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i128 [[TMP1]], 64 ; CHECK-NEXT: [[TMP4:%.*]] = or i128 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = and i128 [[TMP4]], 1 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i64 -; CHECK-NEXT: ret i64 [[TMP6]] +; CHECK-NEXT: ret i128 [[TMP5]] ; %tmp1 = zext i64 %a to i128 %tmp2 = zext i1 %b to i128 %tmp3 = shl nuw i128 %tmp1, 64 %tmp4 = or i128 %tmp2, %tmp3 %tmp5 = and i128 %tmp4, 1 - %tmp6 = trunc i128 %tmp5 to i64 - ret i64 %tmp6 + ret i128 %tmp5 } define i32 @shl_or_and6(i16 %a, i16 %b) { @@ -1109,3 +1105,55 @@ define i32 @shl_or_and8(i16 %a, i16 %b) { %tmp5 = and i32 %tmp4, 131071 ; mask with 0x1FFFF ret i32 %tmp5 } + +define <2 x i64> @shl_or_and1v(<2 x i32> %a, <2 x i1> %b) { +; CHECK-LABEL: @shl_or_and1v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP4]], +; CHECK-NEXT: ret <2 x i64> [[TMP5]] +; + %tmp1 = zext <2 x i32> %a to <2 x i64> + %tmp2 = zext <2 x i1> %b to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, + %tmp4 = or <2 x i64> %tmp2, %tmp3 + %tmp5 = and <2 x i64> %tmp4, + ret <2 x i64> %tmp5 +} + +define <2 x i64> @shl_or_and2v(<2 x i32> %a, <2 x i1> %b) { +; CHECK-LABEL: @shl_or_and2v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP4]], +; CHECK-NEXT: ret <2 x i64> [[TMP5]] +; + %tmp1 = zext <2 x i1> %b to <2 x i64> + %tmp2 = zext <2 x i32> %a to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, + %tmp4 = or <2 x i64> %tmp2, %tmp3 + %tmp5 = and <2 x i64> %tmp4, + ret <2 x i64> %tmp5 +} + +define <2 x i32> @shl_or_and3v(<2 x i16> %a, <2 x i16> %b) { +; A variation of above test case, but fails due to the mask value +; CHECK-LABEL: @shl_or_and3v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[A:%.*]] to <2 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[B:%.*]] to <2 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i32> [[TMP1]], +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i32> [[TMP4]], +; CHECK-NEXT: ret <2 x i32> [[TMP5]] +; + %tmp1 = zext <2 x i16> %a to <2 x i32> + %tmp2 = zext <2 x i16> %b to <2 x i32> + %tmp3 = shl nuw <2 x i32> %tmp1, + %tmp4 = or <2 x i32> %tmp2, %tmp3 + %tmp5 = and <2 x i32> %tmp4, ; mask with 0xFFFF0001 + ret <2 x i32> %tmp5 +} diff --git a/test/Transforms/InstSimplify/shift.ll b/test/Transforms/InstSimplify/shift.ll index 7a09ef97151..1978cfc1f3d 100644 --- a/test/Transforms/InstSimplify/shift.ll +++ b/test/Transforms/InstSimplify/shift.ll @@ -175,26 +175,24 @@ define <2 x i8> @shl_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) { ret <2 x i8> %r } -define i32 @shl_or_shr(i32 %a, i32 %b) { +define i64 @shl_or_shr(i32 %a, i32 %b) { ; CHECK-LABEL: @shl_or_shr( ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 32 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -; CHECK-NEXT: ret i32 [[TMP6]] +; CHECK-NEXT: ret i64 [[TMP5]] ; %tmp1 = zext i32 %a to i64 %tmp2 = zext i32 %b to i64 %tmp3 = shl nuw i64 %tmp1, 32 %tmp4 = or i64 %tmp2, %tmp3 %tmp5 = lshr i64 %tmp4, 32 - %tmp6 = trunc i64 %tmp5 to i32 - ret i32 %tmp6 + ret i64 %tmp5 } -define i32 @shl_or_shr2(i32 %a, i32 %b) { +define i64 @shl_or_shr2(i32 %a, i32 %b) { ; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated. ; CHECK-LABEL: @shl_or_shr2( ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 @@ -202,14 +200,48 @@ define i32 @shl_or_shr2(i32 %a, i32 %b) { ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 31 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 31 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -; CHECK-NEXT: ret i32 [[TMP6]] +; CHECK-NEXT: ret i64 [[TMP5]] ; %tmp1 = zext i32 %a to i64 %tmp2 = zext i32 %b to i64 %tmp3 = shl nuw i64 %tmp1, 31 %tmp4 = or i64 %tmp2, %tmp3 %tmp5 = lshr i64 %tmp4, 31 - %tmp6 = trunc i64 %tmp5 to i32 - ret i32 %tmp6 + ret i64 %tmp5 +} + +define <2 x i64> @shl_or_shr1v(<2 x i32> %a, <2 x i32> %b) { +; Unit test for vector integer +; CHECK-LABEL: @shl_or_shr1v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], +; CHECK-NEXT: ret <2 x i64> [[TMP5]] +; + %tmp1 = zext <2 x i32> %a to <2 x i64> + %tmp2 = zext <2 x i32> %b to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, + %tmp4 = or <2 x i64> %tmp2, %tmp3 + %tmp5 = lshr <2 x i64> %tmp4, + ret <2 x i64> %tmp5 +} + +define <2 x i64> @shl_or_shr2v(<2 x i32> %a, <2 x i32> %b) { +; Negative unit test for vector integer +; CHECK-LABEL: @shl_or_shr2v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], +; CHECK-NEXT: ret <2 x i64> [[TMP5]] +; + %tmp1 = zext <2 x i32> %a to <2 x i64> + %tmp2 = zext <2 x i32> %b to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, + %tmp4 = or <2 x i64> %tmp2, %tmp3 + %tmp5 = lshr <2 x i64> %tmp4, + ret <2 x i64> %tmp5 } -- 2.50.1