From 240366c25ae8d7cc1ba61f16ebbe86f58868720f Mon Sep 17 00:00:00 2001 From: Chen Zheng Date: Wed, 22 May 2019 03:17:39 +0000 Subject: [PATCH] [PowerPC] use meaningful name for displacement form aligned with x-form - NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361347 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstr64Bit.td | 12 +-- lib/Target/PowerPC/PPCInstrInfo.td | 6 +- lib/Target/PowerPC/PPCInstrVSX.td | 136 ++++++++++++++-------------- lib/Target/PowerPC/README_P9.txt | 8 +- 4 files changed, 81 insertions(+), 81 deletions(-) diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 932ab659e4a..78f1cc66a40 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -167,7 +167,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), (ins memrix:$src), "bctrl\n\tld 2, $src", IIC_BrB, - [(PPCbctrl_load_toc ixaddr:$src)]>, + [(PPCbctrl_load_toc iaddrX4:$src)]>, Requires<[In64BitMode]>; } @@ -918,7 +918,7 @@ def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), "lwa $rD, $src", IIC_LdStLWA, [(set i64:$rD, - (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, + (aligned4sextloadi32 iaddrX4:$src))]>, isPPC64, PPC970_DGroup_Cracked; let Interpretation64Bit = 1, isCodeGenOnly = 1 in def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), @@ -1029,7 +1029,7 @@ def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), let PPC970_Unit = 2 in { def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), "ld $rD, $src", IIC_LdStLD, - [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; + [(set i64:$rD, (aligned4load iaddrX4:$src))]>, isPPC64; // The following four definitions are selected for small code model only. // Otherwise, we need to create two instructions to form a 32-bit offset, // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). @@ -1221,7 +1221,7 @@ def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), // Normal 8-byte stores. def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), "std $rS, $dst", IIC_LdStSTD, - [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; + [(aligned4store i64:$rS, iaddrX4:$dst)]>, isPPC64; def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), "stdx $rS, $dst", IIC_LdStSTD, [(store i64:$rS, xaddrX4:$dst)]>, isPPC64, @@ -1440,10 +1440,10 @@ def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), (STDX $rS, xoaddr:$dst)>; // 64-bits atomic loads and stores -def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; +def : Pat<(atomic_load_64 iaddrX4:$src), (LD memrix:$src)>; def : Pat<(atomic_load_64 xaddrX4:$src), (LDX memrr:$src)>; -def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; +def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; def : Pat<(atomic_store_64 xaddrX4:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; let Predicates = [IsISA3_0] in { diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 920f4753189..64511a0c79e 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -895,11 +895,11 @@ def pred : Operand { // Define PowerPC specific addressing mode. // d-form -def iaddr : ComplexPattern; // "stb" +def iaddr : ComplexPattern; // "stb" // ds-form -def ixaddr : ComplexPattern; // "std" +def iaddrX4 : ComplexPattern; // "std" // dq-form -def iqaddr : ComplexPattern; // "stxv" +def iaddrX16 : ComplexPattern; // "stxv" // Below forms are all x-form addressing mode, use three different ones so we // can make a accurate check for x-form instructions in ISEL. diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td index 280f8274d2a..482e5c532b1 100644 --- a/lib/Target/PowerPC/PPCInstrVSX.td +++ b/lib/Target/PowerPC/PPCInstrVSX.td @@ -3037,24 +3037,24 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { } // IsLittleEndian, HasP9Vector // D-Form Load/Store - def : Pat<(v4i32 (quadwOffsetLoad iqaddr:$src)), (LXV memrix16:$src)>; - def : Pat<(v4f32 (quadwOffsetLoad iqaddr:$src)), (LXV memrix16:$src)>; - def : Pat<(v2i64 (quadwOffsetLoad iqaddr:$src)), (LXV memrix16:$src)>; - def : Pat<(v2f64 (quadwOffsetLoad iqaddr:$src)), (LXV memrix16:$src)>; - def : Pat<(f128 (quadwOffsetLoad iqaddr:$src)), + def : Pat<(v4i32 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>; + def : Pat<(v4f32 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>; + def : Pat<(v2i64 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>; + def : Pat<(v2f64 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>; + def : Pat<(f128 (quadwOffsetLoad iaddrX16:$src)), (COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>; - def : Pat<(v4i32 (int_ppc_vsx_lxvw4x iqaddr:$src)), (LXV memrix16:$src)>; - def : Pat<(v2f64 (int_ppc_vsx_lxvd2x iqaddr:$src)), (LXV memrix16:$src)>; + def : Pat<(v4i32 (int_ppc_vsx_lxvw4x iaddrX16:$src)), (LXV memrix16:$src)>; + def : Pat<(v2f64 (int_ppc_vsx_lxvd2x iaddrX16:$src)), (LXV memrix16:$src)>; - def : Pat<(quadwOffsetStore v4f32:$rS, iqaddr:$dst), (STXV $rS, memrix16:$dst)>; - def : Pat<(quadwOffsetStore v4i32:$rS, iqaddr:$dst), (STXV $rS, memrix16:$dst)>; - def : Pat<(quadwOffsetStore v2f64:$rS, iqaddr:$dst), (STXV $rS, memrix16:$dst)>; - def : Pat<(quadwOffsetStore f128:$rS, iqaddr:$dst), + def : Pat<(quadwOffsetStore v4f32:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; + def : Pat<(quadwOffsetStore v4i32:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; + def : Pat<(quadwOffsetStore v2f64:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; + def : Pat<(quadwOffsetStore f128:$rS, iaddrX16:$dst), (STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>; - def : Pat<(quadwOffsetStore v2i64:$rS, iqaddr:$dst), (STXV $rS, memrix16:$dst)>; - def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, iqaddr:$dst), + def : Pat<(quadwOffsetStore v2i64:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; + def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; - def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, iqaddr:$dst), + def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; @@ -3265,41 +3265,41 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src), "#DFLOADf32", - [(set f32:$XT, (load ixaddr:$src))]>; + [(set f32:$XT, (load iaddrX4:$src))]>; def DFLOADf64 : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src), "#DFLOADf64", - [(set f64:$XT, (load ixaddr:$src))]>; + [(set f64:$XT, (load iaddrX4:$src))]>; def DFSTOREf32 : PPCPostRAExpPseudo<(outs), (ins vssrc:$XT, memrix:$dst), "#DFSTOREf32", - [(store f32:$XT, ixaddr:$dst)]>; + [(store f32:$XT, iaddrX4:$dst)]>; def DFSTOREf64 : PPCPostRAExpPseudo<(outs), (ins vsfrc:$XT, memrix:$dst), "#DFSTOREf64", - [(store f64:$XT, ixaddr:$dst)]>; + [(store f64:$XT, iaddrX4:$dst)]>; - def : Pat<(f64 (extloadf32 ixaddr:$src)), - (COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>; - def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))), - (f32 (DFLOADf32 ixaddr:$src))>; + def : Pat<(f64 (extloadf32 iaddrX4:$src)), + (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$src), VSFRC)>; + def : Pat<(f32 (fpround (f64 (extloadf32 iaddrX4:$src)))), + (f32 (DFLOADf32 iaddrX4:$src))>; def : Pat<(v4f32 (PPCldvsxlh xaddr:$src)), (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC)>; - def : Pat<(v4f32 (PPCldvsxlh ixaddr:$src)), - (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC)>; + def : Pat<(v4f32 (PPCldvsxlh iaddrX4:$src)), + (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC)>; let AddedComplexity = 400 in { // The following pseudoinstructions are used to ensure the utilization // of all 64 VSX registers. let Predicates = [IsLittleEndian, HasP9Vector] in { - def : Pat<(v2i64 (scalar_to_vector (i64 (load ixaddr:$src)))), + def : Pat<(v2i64 (scalar_to_vector (i64 (load iaddrX4:$src)))), (v2i64 (XXPERMDIs - (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC), 2))>; + (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC), 2))>; def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddrX4:$src)))), (v2i64 (XXPERMDIs (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC), 2))>; - def : Pat<(v2f64 (scalar_to_vector (f64 (load ixaddr:$src)))), + def : Pat<(v2f64 (scalar_to_vector (f64 (load iaddrX4:$src)))), (v2f64 (XXPERMDIs - (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC), 2))>; + (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC), 2))>; def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddrX4:$src)))), (v2f64 (XXPERMDIs (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC), 2))>; @@ -3313,26 +3313,26 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>; def : Pat<(store (f64 (extractelt v2f64:$A, 1)), xaddrX4:$src), (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>; - def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ixaddr:$src), + def : Pat<(store (i64 (extractelt v2i64:$A, 0)), iaddrX4:$src), (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), - sub_64), ixaddr:$src)>; - def : Pat<(store (f64 (extractelt v2f64:$A, 0)), ixaddr:$src), + sub_64), iaddrX4:$src)>; + def : Pat<(store (f64 (extractelt v2f64:$A, 0)), iaddrX4:$src), (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), - ixaddr:$src)>; - def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ixaddr:$src), - (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ixaddr:$src)>; - def : Pat<(store (f64 (extractelt v2f64:$A, 1)), ixaddr:$src), - (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ixaddr:$src)>; + iaddrX4:$src)>; + def : Pat<(store (i64 (extractelt v2i64:$A, 1)), iaddrX4:$src), + (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>; + def : Pat<(store (f64 (extractelt v2f64:$A, 1)), iaddrX4:$src), + (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>; } // IsLittleEndian, HasP9Vector let Predicates = [IsBigEndian, HasP9Vector] in { - def : Pat<(v2i64 (scalar_to_vector (i64 (load ixaddr:$src)))), - (v2i64 (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC))>; + def : Pat<(v2i64 (scalar_to_vector (i64 (load iaddrX4:$src)))), + (v2i64 (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC))>; def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddrX4:$src)))), (v2i64 (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC))>; - def : Pat<(v2f64 (scalar_to_vector (f64 (load ixaddr:$src)))), - (v2f64 (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC))>; + def : Pat<(v2f64 (scalar_to_vector (f64 (load iaddrX4:$src)))), + (v2f64 (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC))>; def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddrX4:$src)))), (v2f64 (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC))>; def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xaddrX4:$src), @@ -3345,16 +3345,16 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>; def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xaddrX4:$src), (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>; - def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ixaddr:$src), + def : Pat<(store (i64 (extractelt v2i64:$A, 1)), iaddrX4:$src), (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), - sub_64), ixaddr:$src)>; - def : Pat<(store (f64 (extractelt v2f64:$A, 1)), ixaddr:$src), + sub_64), iaddrX4:$src)>; + def : Pat<(store (f64 (extractelt v2f64:$A, 1)), iaddrX4:$src), (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), - sub_64), ixaddr:$src)>; - def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ixaddr:$src), - (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ixaddr:$src)>; - def : Pat<(store (f64 (extractelt v2f64:$A, 0)), ixaddr:$src), - (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ixaddr:$src)>; + sub_64), iaddrX4:$src)>; + def : Pat<(store (i64 (extractelt v2i64:$A, 0)), iaddrX4:$src), + (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>; + def : Pat<(store (f64 (extractelt v2f64:$A, 0)), iaddrX4:$src), + (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>; } // IsBigEndian, HasP9Vector } @@ -3493,12 +3493,12 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { // Convert (Un)Signed DWord in memory -> QP def : Pat<(f128 (sint_to_fp (i64 (load xaddrX4:$src)))), (f128 (XSCVSDQP (LXSDX xaddrX4:$src)))>; - def : Pat<(f128 (sint_to_fp (i64 (load ixaddr:$src)))), - (f128 (XSCVSDQP (LXSD ixaddr:$src)))>; + def : Pat<(f128 (sint_to_fp (i64 (load iaddrX4:$src)))), + (f128 (XSCVSDQP (LXSD iaddrX4:$src)))>; def : Pat<(f128 (uint_to_fp (i64 (load xaddrX4:$src)))), (f128 (XSCVUDQP (LXSDX xaddrX4:$src)))>; - def : Pat<(f128 (uint_to_fp (i64 (load ixaddr:$src)))), - (f128 (XSCVUDQP (LXSD ixaddr:$src)))>; + def : Pat<(f128 (uint_to_fp (i64 (load iaddrX4:$src)))), + (f128 (XSCVUDQP (LXSD iaddrX4:$src)))>; // Convert Unsigned HWord in memory -> QP def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)), @@ -3523,9 +3523,9 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (STXSDX (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), xaddrX4:$dst)>; def : Pat<(PPCstore_scal_int_from_vsr - (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ixaddr:$dst, 8), + (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), iaddrX4:$dst, 8), (STXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), - ixaddr:$dst)>; + iaddrX4:$dst)>; def : Pat<(PPCstore_scal_int_from_vsr (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xoaddr:$dst, 4), (STXSIWX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), xoaddr:$dst)>; @@ -3539,8 +3539,8 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xaddrX4:$dst, 8), (STXSDX (XSCVDPSXDS f64:$src), xaddrX4:$dst)>; def : Pat<(PPCstore_scal_int_from_vsr - (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ixaddr:$dst, 8), - (STXSD (XSCVDPSXDS f64:$src), ixaddr:$dst)>; + (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), iaddrX4:$dst, 8), + (STXSD (XSCVDPSXDS f64:$src), iaddrX4:$dst)>; def : Pat<(PPCstore_scal_int_from_vsr (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 2), (STXSIHX (XSCVDPSXWS f64:$src), xoaddr:$dst)>; @@ -3554,9 +3554,9 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (STXSDX (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), xaddrX4:$dst)>; def : Pat<(PPCstore_scal_int_from_vsr - (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ixaddr:$dst, 8), + (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), iaddrX4:$dst, 8), (STXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), - ixaddr:$dst)>; + iaddrX4:$dst)>; def : Pat<(PPCstore_scal_int_from_vsr (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 4), (STXSIWX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>; @@ -3570,8 +3570,8 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xaddrX4:$dst, 8), (STXSDX (XSCVDPUXDS f64:$src), xaddrX4:$dst)>; def : Pat<(PPCstore_scal_int_from_vsr - (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ixaddr:$dst, 8), - (STXSD (XSCVDPUXDS f64:$src), ixaddr:$dst)>; + (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), iaddrX4:$dst, 8), + (STXSD (XSCVDPUXDS f64:$src), iaddrX4:$dst)>; def : Pat<(PPCstore_scal_int_from_vsr (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 2), (STXSIHX (XSCVDPUXWS f64:$src), xoaddr:$dst)>; @@ -3704,13 +3704,13 @@ def FltToLongLoad { dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 xoaddr:$A))))); } def FltToLongLoadP9 { - dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 ixaddr:$A))))); + dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 iaddrX4:$A))))); } def FltToULongLoad { dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 xoaddr:$A))))); } def FltToULongLoadP9 { - dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 ixaddr:$A))))); + dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 iaddrX4:$A))))); } def FltToLong { dag A = (i64 (PPCmfvsr (f64 (PPCfctidz (fpextend f32:$A))))); @@ -3740,13 +3740,13 @@ def DblToIntLoad { dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load xoaddr:$A))))); } def DblToIntLoadP9 { - dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load ixaddr:$A))))); + dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load iaddrX4:$A))))); } def DblToUIntLoad { dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load xoaddr:$A))))); } def DblToUIntLoadP9 { - dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load ixaddr:$A))))); + dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load iaddrX4:$A))))); } def DblToLongLoad { dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (load xoaddr:$A))))); @@ -4065,17 +4065,17 @@ let AddedComplexity = 400 in { (v4i32 (XVCVSPUXWS (LXVWSX xoaddr:$A)))>; def : Pat<(v4i32 (scalar_to_vector DblToIntLoadP9.A)), (v4i32 (XXSPLTW (COPY_TO_REGCLASS - (XSCVDPSXWS (DFLOADf64 ixaddr:$A)), VSRC), 1))>; + (XSCVDPSXWS (DFLOADf64 iaddrX4:$A)), VSRC), 1))>; def : Pat<(v4i32 (scalar_to_vector DblToUIntLoadP9.A)), (v4i32 (XXSPLTW (COPY_TO_REGCLASS - (XSCVDPUXWS (DFLOADf64 ixaddr:$A)), VSRC), 1))>; + (XSCVDPUXWS (DFLOADf64 iaddrX4:$A)), VSRC), 1))>; def : Pat<(v2i64 (scalar_to_vector FltToLongLoadP9.A)), (v2i64 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS - (DFLOADf32 ixaddr:$A), + (DFLOADf32 iaddrX4:$A), VSFRC)), 0))>; def : Pat<(v2i64 (scalar_to_vector FltToULongLoadP9.A)), (v2i64 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS - (DFLOADf32 ixaddr:$A), + (DFLOADf32 iaddrX4:$A), VSFRC)), 0))>; } diff --git a/lib/Target/PowerPC/README_P9.txt b/lib/Target/PowerPC/README_P9.txt index d56f7cca7b2..c9984b7604b 100644 --- a/lib/Target/PowerPC/README_P9.txt +++ b/lib/Target/PowerPC/README_P9.txt @@ -512,8 +512,8 @@ Fixed Point Facility: "lxsdx $XT, $src", IIC_LdStLFD, [(set f64:$XT, (load xoaddr:$src))]>; - . (set f64:$XT, (load ixaddr:$src)) - (set f64:$XT, (store ixaddr:$dst)) + . (set f64:$XT, (load iaddrX4:$src)) + (set f64:$XT, (store iaddrX4:$dst)) - Load/Store SP, with conversion from/to DP: lxssp stxssp . Similar to lxsspx/stxsspx: @@ -521,8 +521,8 @@ Fixed Point Facility: "lxsspx $XT, $src", IIC_LdStLFD, [(set f32:$XT, (load xoaddr:$src))]>; - . (set f32:$XT, (load ixaddr:$src)) - (set f32:$XT, (store ixaddr:$dst)) + . (set f32:$XT, (load iaddrX4:$src)) + (set f32:$XT, (store iaddrX4:$dst)) - Load as Integer Byte/Halfword & Zero Indexed: lxsibzx lxsihzx . Similar to lxsiwzx: -- 2.50.1