From 23a894cc9eddce42df71c0f3ec68ab73bf7b8182 Mon Sep 17 00:00:00 2001 From: Jinsong Ji Date: Tue, 19 Feb 2019 21:25:13 +0000 Subject: [PATCH] PowerPC: Fix typos in comments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354382 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/P9InstrResources.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/PowerPC/P9InstrResources.td b/lib/Target/PowerPC/P9InstrResources.td index c4c1098c757..4b49d2722d6 100644 --- a/lib/Target/PowerPC/P9InstrResources.td +++ b/lib/Target/PowerPC/P9InstrResources.td @@ -84,7 +84,7 @@ def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C, )>; // Restricted Dispatch ALU operation for 3 cycles. The operation runs on a -// slingle slice. However, since it is Restricted it requires all 3 dispatches +// single slice. However, since it is Restricted it requires all 3 dispatches // (DISP) for that superslice. def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C], (instrs @@ -170,7 +170,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], )>; // Restricted Dispatch ALU operation for 2 cycles. The operation runs on a -// slingle slice. However, since it is Restricted it requires all 3 dispatches +// single slice. However, since it is Restricted it requires all 3 dispatches // (DISP) for that superslice. def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C], (instrs -- 2.50.1