From 238512c3f88b218af7f30acf1f06d8bf456ae5d3 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 8 Dec 2017 20:10:31 +0000 Subject: [PATCH] [X86][X87] Tag x87 float compare instructions scheduler classes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320189 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrFPStack.td | 26 ++++++++++------- test/CodeGen/X86/x87-schedule.ll | 48 +++++++++++++++---------------- 2 files changed, 39 insertions(+), 35 deletions(-) diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index cfc38f0f005..6b41f1456f4 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -281,6 +281,8 @@ def SUB_FPrST0 : FPrST0PInst; def SUB_FST0r : FPST0rInst ; def SUBR_FrST0 : FPrST0Inst ; def SUBR_FPrST0 : FPrST0PInst; +def COM_FST0r : FPST0rInst ; +def COMP_FST0r : FPST0rInst ; } // SchedRW let SchedRW = [WriteFMul] in { def MUL_FST0r : FPST0rInst ; @@ -296,9 +298,6 @@ def DIVR_FrST0 : FPrST0Inst ; def DIVR_FPrST0 : FPrST0PInst; } // SchedRW -def COM_FST0r : FPST0rInst ; -def COMP_FST0r : FPST0rInst ; - // Unary operations. multiclass FPUnary { @@ -326,39 +325,44 @@ defm SIN : FPUnary; defm COS : FPUnary; } +let SchedRW = [WriteFAdd] in { let hasSideEffects = 0 in { def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; } // hasSideEffects -let SchedRW = [WriteFAdd] in def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst", IIC_FCOMI>; +} // SchedRW } // Defs = [FPSW] // Versions of FP instructions that take a single memory operand. Added for the // disassembler; remove as they are included with patterns elsewhere. +let SchedRW = [WriteFAddLd] in { def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; -def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; -def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; +def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; +def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; + +def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; +def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; +} // SchedRW -def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; -def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; +let SchedRW = [WriteMicrocoded] in { +def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; +def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; -def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; -def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; - def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; +} // SchedRW // Floating point cmovs. class FpIf32CMov pattern, diff --git a/test/CodeGen/X86/x87-schedule.ll b/test/CodeGen/X86/x87-schedule.ll index d3d7f2923e9..66cea9c34c4 100644 --- a/test/CodeGen/X86/x87-schedule.ll +++ b/test/CodeGen/X86/x87-schedule.ll @@ -752,10 +752,10 @@ define void @test_fcom(float *%a0, double *%a1) optsize { ; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00] ; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00] ; SLM-NEXT: #APP -; SLM-NEXT: fcom %st(1) -; SLM-NEXT: fcom %st(3) -; SLM-NEXT: fcoms (%ecx) -; SLM-NEXT: fcoml (%eax) +; SLM-NEXT: fcom %st(1) # sched: [3:1.00] +; SLM-NEXT: fcom %st(3) # sched: [3:1.00] +; SLM-NEXT: fcoms (%ecx) # sched: [6:1.00] +; SLM-NEXT: fcoml (%eax) # sched: [6:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retl # sched: [4:1.00] ; @@ -824,10 +824,10 @@ define void @test_fcom(float *%a0, double *%a1) optsize { ; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00] ; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00] ; BTVER2-NEXT: #APP -; BTVER2-NEXT: fcom %st(1) -; BTVER2-NEXT: fcom %st(3) -; BTVER2-NEXT: fcoms (%ecx) -; BTVER2-NEXT: fcoml (%eax) +; BTVER2-NEXT: fcom %st(1) # sched: [3:1.00] +; BTVER2-NEXT: fcom %st(3) # sched: [3:1.00] +; BTVER2-NEXT: fcoms (%ecx) # sched: [8:1.00] +; BTVER2-NEXT: fcoml (%eax) # sched: [8:1.00] ; BTVER2-NEXT: #NO_APP ; BTVER2-NEXT: retl # sched: [4:1.00] ; @@ -878,10 +878,10 @@ define void @test_fcomp_fcompp(float *%a0, double *%a1) optsize { ; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00] ; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00] ; SLM-NEXT: #APP -; SLM-NEXT: fcomp %st(1) -; SLM-NEXT: fcomp %st(3) -; SLM-NEXT: fcomps (%ecx) -; SLM-NEXT: fcompl (%eax) +; SLM-NEXT: fcomp %st(1) # sched: [3:1.00] +; SLM-NEXT: fcomp %st(3) # sched: [3:1.00] +; SLM-NEXT: fcomps (%ecx) # sched: [6:1.00] +; SLM-NEXT: fcompl (%eax) # sched: [6:1.00] ; SLM-NEXT: fcompp # sched: [100:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retl # sched: [4:1.00] @@ -956,10 +956,10 @@ define void @test_fcomp_fcompp(float *%a0, double *%a1) optsize { ; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00] ; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00] ; BTVER2-NEXT: #APP -; BTVER2-NEXT: fcomp %st(1) -; BTVER2-NEXT: fcomp %st(3) -; BTVER2-NEXT: fcomps (%ecx) -; BTVER2-NEXT: fcompl (%eax) +; BTVER2-NEXT: fcomp %st(1) # sched: [3:1.00] +; BTVER2-NEXT: fcomp %st(3) # sched: [3:1.00] +; BTVER2-NEXT: fcomps (%ecx) # sched: [8:1.00] +; BTVER2-NEXT: fcompl (%eax) # sched: [8:1.00] ; BTVER2-NEXT: fcompp # sched: [100:0.17] ; BTVER2-NEXT: #NO_APP ; BTVER2-NEXT: retl # sched: [4:1.00] @@ -1812,10 +1812,10 @@ define void @test_ficom(i16 *%a0, i32 *%a1) optsize { ; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00] ; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00] ; SLM-NEXT: #APP -; SLM-NEXT: ficoms (%ecx) -; SLM-NEXT: ficoml (%eax) -; SLM-NEXT: ficomps (%ecx) -; SLM-NEXT: ficompl (%eax) +; SLM-NEXT: ficoms (%ecx) # sched: [6:1.00] +; SLM-NEXT: ficoml (%eax) # sched: [6:1.00] +; SLM-NEXT: ficomps (%ecx) # sched: [6:1.00] +; SLM-NEXT: ficompl (%eax) # sched: [6:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retl # sched: [4:1.00] ; @@ -1884,10 +1884,10 @@ define void @test_ficom(i16 *%a0, i32 *%a1) optsize { ; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00] ; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00] ; BTVER2-NEXT: #APP -; BTVER2-NEXT: ficoms (%ecx) -; BTVER2-NEXT: ficoml (%eax) -; BTVER2-NEXT: ficomps (%ecx) -; BTVER2-NEXT: ficompl (%eax) +; BTVER2-NEXT: ficoms (%ecx) # sched: [8:1.00] +; BTVER2-NEXT: ficoml (%eax) # sched: [8:1.00] +; BTVER2-NEXT: ficomps (%ecx) # sched: [8:1.00] +; BTVER2-NEXT: ficompl (%eax) # sched: [8:1.00] ; BTVER2-NEXT: #NO_APP ; BTVER2-NEXT: retl # sched: [4:1.00] ; -- 2.50.0