From 21f0df75f5bac02619fb6fa4bcf5b49b169aeb1a Mon Sep 17 00:00:00 2001
From: Elijah Taylor <elijahtaylor@google.com>
Date: Thu, 31 Jan 2013 14:00:58 -0800
Subject: [PATCH] NaCl ARM work, first pass

---
 include/private/gc_locks.h | 13 ++++++++++++-
 include/private/gcconfig.h | 10 ++++++++--
 pthread_stop_world.c       | 16 ++++++++++++++++
 3 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/include/private/gc_locks.h b/include/private/gc_locks.h
index 8705d07a..80712fcd 100644
--- a/include/private/gc_locks.h
+++ b/include/private/gc_locks.h
@@ -223,12 +223,22 @@
 #       define GC_CLEAR_DEFINED
 #    endif /* ALPHA */
 #    ifdef ARM32
+#ifdef __native_client__
+#define NACL_ALIGN() ".align 4\n"
+#define MASK_REGISTER(reg) "bic " reg ", " reg ", #0xc0000000\n"
+#else
+#define NACL_ALIGN()
+#define MASK_REGISTER(reg)
+#endif
         inline static int GC_test_and_set(volatile unsigned int *addr) {
 #if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__)
           int ret, tmp;
           __asm__ __volatile__ (
                                  "1:\n"
+                                 NACL_ALIGN()
+                                 MASK_REGISTER("%3")
                                  "ldrex %0, [%3]\n"
+                                 MASK_REGISTER("%3")
                                  "strex %1, %2, [%3]\n" 
                                  "teq %1, #0\n"
                                  "bne 1b\n"
@@ -242,7 +252,8 @@
            * bus because there are no SMP ARM machines.  If/when there are,
            * this code will likely need to be updated. */
           /* See linuxthreads/sysdeps/arm/pt-machine.h in glibc-2.1 */
-          __asm__ __volatile__("swp %0, %1, [%2]"
+          __asm__ __volatile__(MASK_REGISTER("%2")
+                               "swp %0, %1, [%2]"
       		  	     : "=&r"(oldval)
       			     : "r"(1), "r"(addr)
 			     : "memory");
diff --git a/include/private/gcconfig.h b/include/private/gcconfig.h
index 49ffccdd..88e78380 100644
--- a/include/private/gcconfig.h
+++ b/include/private/gcconfig.h
@@ -76,7 +76,9 @@
 # endif
 # if defined(__arm__) || defined(__thumb__)
 #    define ARM32
-#    if !defined(LINUX) && !defined(NETBSD) && !defined(DARWIN)
+#    if defined(NACL)
+#      define mach_type_known
+#    elif !defined(LINUX) && !defined(NETBSD) && !defined(DARWIN)
 #      define NOSYS
 #      define mach_type_known
 #    endif
@@ -1926,8 +1928,12 @@
 # endif
 
 # ifdef ARM32
-#   define CPP_WORDSZ 32
+# if defined( NACL )
+#   define MACH_TYPE "NACL"
+# else
 #   define MACH_TYPE "ARM32"
+# endif
+#   define CPP_WORDSZ 32
 #   define ALIGNMENT 4
 #   ifdef NETBSD
 #       define OS_TYPE "NETBSD"
diff --git a/pthread_stop_world.c b/pthread_stop_world.c
index 8b25376b..fe2ba1a3 100644
--- a/pthread_stop_world.c
+++ b/pthread_stop_world.c
@@ -537,6 +537,22 @@ static void pthread_stop_world()
 	__asm__ __volatile__ ("add $16, %esp");\
     } while (0)
 
+#elif __arm__
+
+#define NACL_STORE_REGS()  \
+    do {                  \
+	__asm__ __volatile__ ("push {r4-r12,lr}");\
+	__asm__ __volatile__ ("mov r0, %0" : : "r" (&nacl_gc_thread_self->stop_info.stack_ptr)); \
+	__asm__ __volatile__ ("bic r0, r0, #0xc0000000");\
+	__asm__ __volatile__ ("str sp, [r0]");\
+	memcpy(nacl_gc_thread_self->stop_info.reg_storage, nacl_gc_thread_self->stop_info.stack_ptr, NACL_GC_REG_STORAGE_SIZE * sizeof(ptr_t));\
+	__asm__ __volatile__ ("add sp, sp, #40");\
+	__asm__ __volatile__ ("bic sp, sp, #0xc0000000");\
+    } while (0)
+#else
+
+#error "Please port NACL_STORE_REGS"
+
 #endif
 
 void nacl_pre_syscall_hook()
-- 
2.40.0