From 2146c5ac40a34b49bab1136e93368c455f263abc Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 28 Oct 2017 17:59:56 +0000 Subject: [PATCH] [X86][SSE] Rename truncateVectorCompareWithPACKSS to truncateVectorWithPACKSS. NFC. We no longer rely on the vector source being a comparison result, just have sufficient sign bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316834 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 53bc6adf601..8c29801aedb 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -15990,14 +15990,13 @@ static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget &Subtarget, } /// Helper to recursively truncate vector elements in half with PACKSS. -/// It makes use of the fact that vector comparison results will be all-zeros -/// or all-ones to prevent the PACKSS from saturating the results. +/// It makes use of the fact that vectors with enough leading sign bits +/// prevent the PACKSS from saturating the results. /// AVX2 (Int256) sub-targets require extra shuffling as the PACKSS operates /// within each 128-bit lane. -static SDValue truncateVectorCompareWithPACKSS(EVT DstVT, SDValue In, - const SDLoc &DL, - SelectionDAG &DAG, - const X86Subtarget &Subtarget) { +static SDValue truncateVectorWithPACKSS(EVT DstVT, SDValue In, const SDLoc &DL, + SelectionDAG &DAG, + const X86Subtarget &Subtarget) { // Requires SSE2 but AVX512 has fast truncate. if (!Subtarget.hasSSE2() || Subtarget.hasAVX512()) return SDValue(); @@ -16065,18 +16064,18 @@ static SDValue truncateVectorCompareWithPACKSS(EVT DstVT, SDValue In, // If 512bit -> 128bit truncate another stage. EVT PackedVT = EVT::getVectorVT(Ctx, PackedSVT, NumElems); Res = DAG.getBitcast(PackedVT, Res); - return truncateVectorCompareWithPACKSS(DstVT, Res, DL, DAG, Subtarget); + return truncateVectorWithPACKSS(DstVT, Res, DL, DAG, Subtarget); } // Recursively pack lower/upper subvectors, concat result and pack again. assert(SrcSizeInBits >= 512 && "Expected 512-bit vector or greater"); EVT PackedVT = EVT::getVectorVT(Ctx, PackedSVT, NumSubElts); - Lo = truncateVectorCompareWithPACKSS(PackedVT, Lo, DL, DAG, Subtarget); - Hi = truncateVectorCompareWithPACKSS(PackedVT, Hi, DL, DAG, Subtarget); + Lo = truncateVectorWithPACKSS(PackedVT, Lo, DL, DAG, Subtarget); + Hi = truncateVectorWithPACKSS(PackedVT, Hi, DL, DAG, Subtarget); PackedVT = EVT::getVectorVT(Ctx, PackedSVT, NumElems); SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedVT, Lo, Hi); - return truncateVectorCompareWithPACKSS(DstVT, Res, DL, DAG, Subtarget); + return truncateVectorWithPACKSS(DstVT, Res, DL, DAG, Subtarget); } static SDValue LowerTruncateVecI1(SDValue Op, SelectionDAG &DAG, @@ -16140,7 +16139,7 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const { // Truncate with PACKSS if we are truncating a vector zero/all-bits result. if (InVT.getScalarSizeInBits() == DAG.ComputeNumSignBits(In)) - if (SDValue V = truncateVectorCompareWithPACKSS(VT, In, DL, DAG, Subtarget)) + if (SDValue V = truncateVectorWithPACKSS(VT, In, DL, DAG, Subtarget)) return V; if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) { @@ -34328,7 +34327,7 @@ static SDValue combineVectorSignBitsTruncation(SDNode *N, SDLoc &DL, if (InSVT != MVT::i16 && InSVT != MVT::i32 && InSVT != MVT::i64) return SDValue(); - return truncateVectorCompareWithPACKSS(VT, In, DL, DAG, Subtarget); + return truncateVectorWithPACKSS(VT, In, DL, DAG, Subtarget); } static SDValue combineTruncate(SDNode *N, SelectionDAG &DAG, -- 2.40.0