From 21027f253e95f4d39e7e10f7373d190bd7bc9c1c Mon Sep 17 00:00:00 2001 From: "Ivan A. Kosarev" Date: Wed, 11 Apr 2018 14:43:11 +0000 Subject: [PATCH] [NEON] Support vfma_n and vfms_n intrinsics Differential Revision: https://reviews.llvm.org/D45483 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@329814 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/clang/Basic/arm_neon.td | 4 ++-- test/CodeGen/aarch64-neon-2velem.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td index 28a763c071..94d39e92f2 100644 --- a/include/clang/Basic/arm_neon.td +++ b/include/clang/Basic/arm_neon.td @@ -621,8 +621,8 @@ def FMLS : SOpInst<"vfms", "dddd", "dQd", OP_FMLS>; // MUL, MLA, MLS, FMA, FMS definitions with scalar argument def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>; -def FMLA_N : SOpInst<"vfma_n", "ddds", "fQfQd", OP_FMLA_N>; -def FMLS_N : SOpInst<"vfms_n", "ddds", "fQfQd", OP_FMLS_N>; +def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>; +def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>; def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>; def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>; diff --git a/test/CodeGen/aarch64-neon-2velem.c b/test/CodeGen/aarch64-neon-2velem.c index 3867b01afb..320ce0286b 100644 --- a/test/CodeGen/aarch64-neon-2velem.c +++ b/test/CodeGen/aarch64-neon-2velem.c @@ -3083,6 +3083,17 @@ float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) { return vfma_n_f32(a, b, n); } +// CHECK-LABEL: @test_vfma_n_f64( +// CHECK: [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, i32 0 +// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> +// CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8> +// CHECK: [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8> +// CHECK: [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> [[VECINIT_I]], <1 x double> %a) +// CHECK: ret <1 x double> [[TMP3]] +float64x1_t test_vfma_n_f64(float64x1_t a, float64x1_t b, float64_t n) { + return vfma_n_f64(a, b, n); +} + // CHECK-LABEL: @test_vfmaq_n_f32( // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1 @@ -3110,6 +3121,18 @@ float32x2_t test_vfms_n_f32(float32x2_t a, float32x2_t b, float32_t n) { return vfms_n_f32(a, b, n); } +// CHECK-LABEL: @test_vfms_n_f64( +// CHECK: [[SUB_I:%.*]] = fsub <1 x double> , %b +// CHECK: [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, i32 0 +// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> +// CHECK: [[TMP1:%.*]] = bitcast <1 x double> [[SUB_I]] to <8 x i8> +// CHECK: [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8> +// CHECK: [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> [[SUB_I]], <1 x double> [[VECINIT_I]], <1 x double> %a) +// CHECK: ret <1 x double> [[TMP3]] +float64x1_t test_vfms_n_f64(float64x1_t a, float64x1_t b, float64_t n) { + return vfms_n_f64(a, b, n); +} + // CHECK-LABEL: @test_vfmsq_n_f32( // CHECK: [[SUB_I:%.*]] = fsub <4 x float> , %b // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0 -- 2.40.0