From 2052d938aa4adb2f1a82dddef7c02aa9d115fd89 Mon Sep 17 00:00:00 2001
From: Hal Finkel <hfinkel@anl.gov>
Date: Sun, 2 Mar 2014 18:24:18 +0000
Subject: [PATCH] Add a PPC inline asm constraint type for single CR bits

This adds support for the PPC "wc" inline asm constraint (used for allocating
individual CR bits). Support for this constraint type was recently added to the
LLVM PowerPC backend. Although gcc does not currently support allocating
individual CR bits, this identifier choice has been coordinated with the gcc
PowerPC team, and will be marked as reserved for this purpose in the gcc
constraints.md file.

Prior to this change, none of the multi-character PPC constraints were handled
correctly (the '^' escape character was not being added as required by the
parsing code in LLVM). This should now be fixed. I'll add tests for these other
constraints as support is added for them in the backend.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@202658 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Basic/Targets.cpp           | 15 +++++++++++++++
 test/CodeGen/ppc64-inline-asm.c | 26 ++++++++++++++++++++++++++
 2 files changed, 41 insertions(+)
 create mode 100644 test/CodeGen/ppc64-inline-asm.c

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 4a87717693..1a59ec6208 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -788,6 +788,7 @@ public:
         case 'f':// VSX vector register to hold vector float data
         case 's':// VSX vector register to hold scalar float data
         case 'a':// Any VSX register
+        case 'c':// An individual CR bit
           break;
         default:
           return false;
@@ -863,6 +864,20 @@ public:
     }
     return true;
   }
+  virtual std::string convertConstraint(const char *&Constraint) const {
+    std::string R;
+    switch (*Constraint) {
+    case 'e':
+    case 'w':
+      // Two-character constraint; add "^" hint for later parsing.
+      R = std::string("^") + std::string(Constraint, 2);
+      Constraint++;
+      break;
+    default:
+      return TargetInfo::convertConstraint(Constraint);
+    }
+    return R;
+  }
   virtual const char *getClobbers() const {
     return "";
   }
diff --git a/test/CodeGen/ppc64-inline-asm.c b/test/CodeGen/ppc64-inline-asm.c
new file mode 100644
index 0000000000..552fe280e0
--- /dev/null
+++ b/test/CodeGen/ppc64-inline-asm.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -O2 -emit-llvm -o - %s | FileCheck %s
+
+_Bool test_wc_i1(_Bool b1, _Bool b2) {
+  _Bool o;
+  asm("crand %0, %1, %2" : "=wc"(o) : "wc"(b1), "wc"(b2) : );
+  return o;
+// CHECK-LABEL: define zeroext i1 @test_wc_i1(i1 zeroext %b1, i1 zeroext %b2)
+// CHECK: call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2)
+}
+
+int test_wc_i32(int b1, int b2) {
+  int o;
+  asm("crand %0, %1, %2" : "=wc"(o) : "wc"(b1), "wc"(b2) : );
+  return o;
+// CHECK-LABEL: signext i32 @test_wc_i32(i32 signext %b1, i32 signext %b2)
+// CHECK: call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2)
+}
+
+unsigned char test_wc_i8(unsigned char b1, unsigned char b2) {
+  unsigned char o;
+  asm("crand %0, %1, %2" : "=wc"(o) : "wc"(b1), "wc"(b2) : );
+  return o;
+// CHECK-LABEL: zeroext i8 @test_wc_i8(i8 zeroext %b1, i8 zeroext %b2)
+// CHECK: call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2)
+}
+
-- 
2.40.0