From 1e96d00f3f31feaaaa2f87d7d47eb92dec23ecb5 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 May 2019 12:25:46 +0000 Subject: [PATCH] [Hexagon] assert getRegisterBitWidth returns non-zero value. NFCI. Fixes scan-build warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361375 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonTargetTransformInfo.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp index c817cb1842d..38062e8e922 100644 --- a/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp +++ b/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp @@ -160,14 +160,15 @@ unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned VecWidth = VecTy->getBitWidth(); if (useHVX() && isTypeForHVX(VecTy)) { unsigned RegWidth = getRegisterBitWidth(true); - Alignment = std::min(Alignment, RegWidth/8); + assert(RegWidth && "Non-zero vector register width expected"); // Cost of HVX loads. if (VecWidth % RegWidth == 0) return VecWidth / RegWidth; // Cost of constructing HVX vector from scalar loads. + Alignment = std::min(Alignment, RegWidth / 8); unsigned AlignWidth = 8 * std::max(1u, Alignment); unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth; - return 3*NumLoads; + return 3 * NumLoads; } // Non-HVX vectors. -- 2.50.1