From 1da64d70383daba234ad596fee54208efcbcad23 Mon Sep 17 00:00:00 2001 From: Pablo Barrio Date: Mon, 30 Sep 2019 16:55:10 +0000 Subject: [PATCH] Fix doc for t inline asm constraints for ARM/Thumb Summary: The constraint goes up to regs d15 and q7, not d16 and q8. Subscribers: kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68090 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373228 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/LangRef.rst | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/docs/LangRef.rst b/docs/LangRef.rst index 70f97c25646..2d4c57b7968 100644 --- a/docs/LangRef.rst +++ b/docs/LangRef.rst @@ -3862,12 +3862,12 @@ ARM and ARM's Thumb2 mode: as ``r``. - ``h``: In Thumb2 mode, a high 32-bit GPR register (``r8-r15``). In ARM mode, invalid. -- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``, - ``d0-d31``, or ``q0-q15``. -- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``, - ``d0-d7``, or ``q0-q3``. -- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or - ``q0-q8``. +- ``w``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s31``, ``d0-d31``, or ``q0-q15``, respectively. +- ``t``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s31``, ``d0-d15``, or ``q0-q7``, respectively. +- ``x``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s15``, ``d0-d7``, or ``q0-q3``, respectively. ARM's Thumb1 mode: @@ -3882,12 +3882,12 @@ ARM's Thumb1 mode: - ``r``: A low 32-bit GPR register (``r0-r7``). - ``l``: A low 32-bit GPR register (``r0-r7``). - ``h``: A high GPR register (``r0-r7``). -- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``, - ``d0-d31``, or ``q0-q15``. -- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``, - ``d0-d7``, or ``q0-q3``. -- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or - ``q0-q8``. +- ``w``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s31``, ``d0-d31``, or ``q0-q15``, respectively. +- ``t``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s31``, ``d0-d15``, or ``q0-q7``, respectively. +- ``x``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges + ``s0-s15``, ``d0-d7``, or ``q0-q3``, respectively. Hexagon: -- 2.40.0