From 1adf22dd67e7c861b37c9f366c14a391ebfb6ced Mon Sep 17 00:00:00 2001 From: Peter Johnson Date: Sun, 12 Sep 2004 21:06:45 +0000 Subject: [PATCH] * yasm_arch.xml, yasm_arch.7: Fix typo in 64-bit implicit zero extension example code. Noticed by: mu@ svn path=/trunk/yasm/; revision=1145 --- modules/arch/yasm_arch.7 | 2 +- modules/arch/yasm_arch.xml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/modules/arch/yasm_arch.7 b/modules/arch/yasm_arch.7 index b1c36d0f..24eae9de 100644 --- a/modules/arch/yasm_arch.7 +++ b/modules/arch/yasm_arch.7 @@ -90,7 +90,7 @@ Results of 32\-bit operations are implicitly zero\-extended to the upper 32 bits .IP mov ecx, 1 ; 1 byte shorter than mov rcx, 1 .IP -and edx, 3 ; equivalent to and rdx, 5 +and edx, 3 ; equivalent to and rdx, 3 .PP For most instructions in 64\-bit mode, immediate values remain 32 bits; their value is sign\-extended into the upper 32 bits of the target register prior to being used\&. The exception is the mov instruction, which can take a 64\-bit immediate when the destination is a 64\-bit register\&. Examples in NASM syntax: diff --git a/modules/arch/yasm_arch.xml b/modules/arch/yasm_arch.xml index dacf2cc1..4b0cc0fd 100644 --- a/modules/arch/yasm_arch.xml +++ b/modules/arch/yasm_arch.xml @@ -169,7 +169,7 @@ Examples in NASM syntax: mov ecx, 1 ; 1 byte shorter than mov rcx, 1 - and edx, 3 ; equivalent to and rdx, 5 + and edx, 3 ; equivalent to and rdx, 3 -- 2.40.0