From 1a7747f8cfad5892896a484fbfc971d82724c6b6 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Fri, 5 Jul 2019 12:16:40 +0000 Subject: [PATCH] [RISCV][NFC] Replace hard-coded CSR duplication with symbolic references Reviewers: asb, lenary Reviewed By: asb, lenary Subscribers: MaskRay, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64139 Patch by James Clarke (jrtc27) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365195 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/RISCV/RISCV.td | 12 +++++----- lib/Target/RISCV/RISCVInstrInfo.td | 14 +++++------ lib/Target/RISCV/RISCVInstrInfoF.td | 31 ++++++++++++------------- lib/Target/RISCV/RISCVSystemOperands.td | 18 +++++++------- 4 files changed, 36 insertions(+), 39 deletions(-) diff --git a/lib/Target/RISCV/RISCV.td b/lib/Target/RISCV/RISCV.td index b166418a622..e19b70b8e70 100644 --- a/lib/Target/RISCV/RISCV.td +++ b/lib/Target/RISCV/RISCV.td @@ -65,18 +65,18 @@ def FeatureRelax "Enable Linker relaxation.">; //===----------------------------------------------------------------------===// -// Registers, calling conventions, instruction descriptions. +// Named operands for CSR instructions. //===----------------------------------------------------------------------===// -include "RISCVRegisterInfo.td" -include "RISCVCallingConv.td" -include "RISCVInstrInfo.td" +include "RISCVSystemOperands.td" //===----------------------------------------------------------------------===// -// Named operands for CSR instructions. +// Registers, calling conventions, instruction descriptions. //===----------------------------------------------------------------------===// -include "RISCVSystemOperands.td" +include "RISCVRegisterInfo.td" +include "RISCVCallingConv.td" +include "RISCVInstrInfo.td" //===----------------------------------------------------------------------===// // RISC-V processors supported. diff --git a/lib/Target/RISCV/RISCVInstrInfo.td b/lib/Target/RISCV/RISCVInstrInfo.td index c181f3a3d05..87a59220d43 100644 --- a/lib/Target/RISCV/RISCVInstrInfo.td +++ b/lib/Target/RISCV/RISCVInstrInfo.td @@ -608,16 +608,14 @@ def : InstAlias<"ret", (JALR X0, X1, 0), 2>; def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw -// CSR Addresses: 0xC00 == cycle, 0xC01 == time, 0xC02 == instret -// 0xC80 == cycleh, 0xC81 == timeh, 0xC82 == instreth -def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, 0xC02, X0)>; -def : InstAlias<"rdcycle $rd", (CSRRS GPR:$rd, 0xC00, X0)>; -def : InstAlias<"rdtime $rd", (CSRRS GPR:$rd, 0xC01, X0)>; +def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, INSTRET.Encoding, X0)>; +def : InstAlias<"rdcycle $rd", (CSRRS GPR:$rd, CYCLE.Encoding, X0)>; +def : InstAlias<"rdtime $rd", (CSRRS GPR:$rd, TIME.Encoding, X0)>; let Predicates = [IsRV32] in { -def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, 0xC82, X0)>; -def : InstAlias<"rdcycleh $rd", (CSRRS GPR:$rd, 0xC80, X0)>; -def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, 0xC81, X0)>; +def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, INSTRETH.Encoding, X0)>; +def : InstAlias<"rdcycleh $rd", (CSRRS GPR:$rd, CYCLEH.Encoding, X0)>; +def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, TIMEH.Encoding, X0)>; } // Predicates = [IsRV32] def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>; diff --git a/lib/Target/RISCV/RISCVInstrInfoF.td b/lib/Target/RISCV/RISCVInstrInfoF.td index 7c957a9bbe5..032642942f2 100644 --- a/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/lib/Target/RISCV/RISCVInstrInfoF.td @@ -222,23 +222,22 @@ def : InstAlias<"fge.s $rd, $rs, $rt", // The following csr instructions actually alias instructions from the base ISA. // However, it only makes sense to support them when the F extension is enabled. -// CSR Addresses: 0x003 == fcsr, 0x002 == frm, 0x001 == fflags // NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr". -def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, 0x003, X0), 2>; -def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, 0x003, GPR:$rs)>; -def : InstAlias<"fscsr $rs", (CSRRW X0, 0x003, GPR:$rs), 2>; - -def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, 0x002, X0), 2>; -def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, 0x002, GPR:$rs)>; -def : InstAlias<"fsrm $rs", (CSRRW X0, 0x002, GPR:$rs), 2>; -def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, 0x002, uimm5:$imm)>; -def : InstAlias<"fsrmi $imm", (CSRRWI X0, 0x002, uimm5:$imm), 2>; - -def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, 0x001, X0), 2>; -def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, 0x001, GPR:$rs)>; -def : InstAlias<"fsflags $rs", (CSRRW X0, 0x001, GPR:$rs), 2>; -def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, 0x001, uimm5:$imm)>; -def : InstAlias<"fsflagsi $imm", (CSRRWI X0, 0x001, uimm5:$imm), 2>; +def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 2>; +def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs)>; +def : InstAlias<"fscsr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 2>; + +def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, FRM.Encoding, X0), 2>; +def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, FRM.Encoding, GPR:$rs)>; +def : InstAlias<"fsrm $rs", (CSRRW X0, FRM.Encoding, GPR:$rs), 2>; +def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, FRM.Encoding, uimm5:$imm)>; +def : InstAlias<"fsrmi $imm", (CSRRWI X0, FRM.Encoding, uimm5:$imm), 2>; + +def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, FFLAGS.Encoding, X0), 2>; +def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, FFLAGS.Encoding, GPR:$rs)>; +def : InstAlias<"fsflags $rs", (CSRRW X0, FFLAGS.Encoding, GPR:$rs), 2>; +def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, FFLAGS.Encoding, uimm5:$imm)>; +def : InstAlias<"fsflagsi $imm", (CSRRWI X0, FFLAGS.Encoding, uimm5:$imm), 2>; // fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both // spellings should be supported by standard tools. diff --git a/lib/Target/RISCV/RISCVSystemOperands.td b/lib/Target/RISCV/RISCVSystemOperands.td index df8cdcc84dc..a46a32c4e7f 100644 --- a/lib/Target/RISCV/RISCVSystemOperands.td +++ b/lib/Target/RISCV/RISCVSystemOperands.td @@ -71,16 +71,16 @@ def : SysReg<"uip", 0x044>; // User Floating-Point CSRs //===-------------------------- -def : SysReg<"fflags", 0x001>; -def : SysReg<"frm", 0x002>; -def : SysReg<"fcsr", 0x003>; +def FFLAGS : SysReg<"fflags", 0x001>; +def FRM : SysReg<"frm", 0x002>; +def FCSR : SysReg<"fcsr", 0x003>; //===-------------------------- // User Counter/Timers //===-------------------------- -def : SysReg<"cycle", 0xC00>; -def : SysReg<"time", 0xC01>; -def : SysReg<"instret", 0xC02>; +def CYCLE : SysReg<"cycle", 0xC00>; +def TIME : SysReg<"time", 0xC01>; +def INSTRET : SysReg<"instret", 0xC02>; def : SysReg<"hpmcounter3", 0xC03>; def : SysReg<"hpmcounter4", 0xC04>; @@ -113,9 +113,9 @@ def : SysReg<"hpmcounter30", 0xC1E>; def : SysReg<"hpmcounter31", 0xC1F>; let isRV32Only = 1 in { -def: SysReg<"cycleh", 0xC80>; -def: SysReg<"timeh", 0xC81>; -def: SysReg<"instreth", 0xC82>; +def CYCLEH : SysReg<"cycleh", 0xC80>; +def TIMEH : SysReg<"timeh", 0xC81>; +def INSTRETH : SysReg<"instreth", 0xC82>; def: SysReg<"hpmcounter3h", 0xC83>; def: SysReg<"hpmcounter4h", 0xC84>; -- 2.40.0