From 18acf60a17f0d12c6a340aa00f4b6f8d5b0b6b8f Mon Sep 17 00:00:00 2001
From: Hrvoje Varga <Hrvoje.Varga@imgtec.com>
Date: Tue, 29 Mar 2016 12:46:16 +0000
Subject: [PATCH] Add additional Hi/Lo registers to Clang MipsTargetInfoBase
 Differential Revision: http://reviews.llvm.org/D17378

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@264727 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Basic/Targets.cpp          |  3 ++-
 test/CodeGen/mips-inline-asm.c | 12 ++++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 95c9a6e56e..f6bb8a5b0e 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -6899,7 +6899,8 @@ public:
       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
       // Hi/lo and condition register names
       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
-      "$fcc5","$fcc6","$fcc7",
+      "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
+      "$ac3hi","$ac3lo",
       // MSA register names
       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
diff --git a/test/CodeGen/mips-inline-asm.c b/test/CodeGen/mips-inline-asm.c
index 2cfa41c98d..fa38663f38 100644
--- a/test/CodeGen/mips-inline-asm.c
+++ b/test/CodeGen/mips-inline-asm.c
@@ -17,3 +17,15 @@ void R () {
   asm("lw $1, %0" :: "R"(data));
   // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data)
 }
+
+int additionalClobberedRegisters () {
+  int temp0;
+  asm volatile(
+                "mfhi %[temp0], $ac1 \n\t"
+                  : [temp0]"=&r"(temp0)
+                  :
+                  : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", "$ac3lo"
+  );
+  return 0;
+  // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", "=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}"
+}
-- 
2.40.0