From 16fb14874c4bd40063a26895c4bbafe7cd42042d Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 6 Jun 2019 07:58:37 +0000 Subject: [PATCH] [AArch64][GlobalISel] Add manual selection support for G_ZEXTLOADs to s64. We already get support for G_ZEXTLOAD to s32 from the importer, but it can't deal with the SUBREG_TO_REG in the pattern. Tweaking the existing manual selection code for G_LOAD to handle an additional SUBREG_TO_REG when dealing with G_ZEXTLOAD isn't much work. Also add tests to check the imported pattern selections to s32 work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362681 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../AArch64/AArch64InstructionSelector.cpp | 23 +++ .../AArch64/GlobalISel/select-zextload.mir | 139 +++++++++++++++++- 2 files changed, 157 insertions(+), 5 deletions(-) diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index 288ef2abed2..df9fd739f57 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1392,8 +1392,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I, return constrainSelectedInstRegOperands(I, TII, TRI, RBI); } + case TargetOpcode::G_ZEXTLOAD: case TargetOpcode::G_LOAD: case TargetOpcode::G_STORE: { + bool IsZExtLoad = I.getOpcode() == TargetOpcode::G_ZEXTLOAD; + MachineIRBuilder MIB(I); + LLT PtrTy = MRI.getType(I.getOperand(1).getReg()); if (PtrTy != LLT::pointer(0, 64)) { @@ -1464,6 +1468,25 @@ bool AArch64InstructionSelector::select(MachineInstr &I, } } + if (IsZExtLoad) { + // The zextload from a smaller type to i32 should be handled by the importer. + if (MRI.getType(ValReg).getSizeInBits() != 64) + return false; + // If we have a ZEXTLOAD then change the load's type to be a narrower reg + //and zero_extend with SUBREG_TO_REG. + unsigned LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); + unsigned DstReg = I.getOperand(0).getReg(); + I.getOperand(0).setReg(LdReg); + + MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator())); + MIB.buildInstr(AArch64::SUBREG_TO_REG, {DstReg}, {}) + .addImm(0) + .addUse(LdReg) + .addImm(AArch64::sub_32); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return RBI.constrainGenericRegister(DstReg, AArch64::GPR64allRegClass, + MRI); + } return constrainSelectedInstRegOperands(I, TII, TRI, RBI); } diff --git a/test/CodeGen/AArch64/GlobalISel/select-zextload.mir b/test/CodeGen/AArch64/GlobalISel/select-zextload.mir index 8d38ac6d317..70dc4718a3c 100644 --- a/test/CodeGen/AArch64/GlobalISel/select-zextload.mir +++ b/test/CodeGen/AArch64/GlobalISel/select-zextload.mir @@ -6,6 +6,37 @@ define void @zextload_s32_from_s16(i16 *%addr) { ret void } define void @zextload_s32_from_s16_not_combined(i16 *%addr) { ret void } + + define i64 @i32_to_i64(i32* %ptr) { + %ld = load i32, i32* %ptr, align 4 + %val = zext i32 %ld to i64 + ret i64 %val + } + + define i64 @i16_to_i64(i16* %ptr) { + %ld = load i16, i16* %ptr, align 2 + %val = zext i16 %ld to i64 + ret i64 %val + } + + define i64 @i8_to_i64(i8* %ptr) { + %ld = load i8, i8* %ptr, align 1 + %val = zext i8 %ld to i64 + ret i64 %val + } + + define i32 @i8_to_i32(i8* %ptr) { + %ld = load i8, i8* %ptr, align 1 + %val = zext i8 %ld to i32 + ret i32 %val + } + + define i32 @i16_to_i32(i16* %ptr) { + %ld = load i16, i16* %ptr, align 2 + %val = zext i16 %ld to i32 + ret i32 %val + } + ... --- @@ -19,8 +50,8 @@ body: | ; CHECK-LABEL: name: zextload_s32_from_s16 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) - ; CHECK: $w0 = COPY [[T0]] + ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) + ; CHECK: $w0 = COPY [[LDRHHui]] %0:gpr(p0) = COPY $x0 %1:gpr(s32) = G_ZEXTLOAD %0 :: (load 2 from %ir.addr) $w0 = COPY %1(s32) @@ -36,11 +67,109 @@ body: | ; CHECK-LABEL: name: zextload_s32_from_s16_not_combined ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) - ; CHECK: [[T1:%[0-9]+]]:gpr32 = UBFMWri [[T0]], 0, 15 - ; CHECK: $w0 = COPY [[T1]] + ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) + ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[LDRHHui]], 0, 15 + ; CHECK: $w0 = COPY [[UBFMWri]] %0:gpr(p0) = COPY $x0 %1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr) %2:gpr(s32) = G_ZEXT %1 $w0 = COPY %2(s32) ... +--- +name: i32_to_i64 +legalized: true +regBankSelected: true +body: | + bb.1 (%ir-block.0): + liveins: $x0 + + ; CHECK-LABEL: name: i32_to_i64 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from %ir.ptr) + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32 + ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] + ; CHECK: RET_ReallyLR implicit $x0 + %0:gpr(p0) = COPY $x0 + %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.ptr) + $x0 = COPY %2(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: i16_to_i64 +legalized: true +regBankSelected: true +body: | + bb.1 (%ir-block.0): + liveins: $x0 + + ; CHECK-LABEL: name: i16_to_i64 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.ptr) + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRHHui]], %subreg.sub_32 + ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] + ; CHECK: RET_ReallyLR implicit $x0 + %0:gpr(p0) = COPY $x0 + %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load 2 from %ir.ptr) + $x0 = COPY %2(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: i8_to_i64 +legalized: true +regBankSelected: true +body: | + bb.1 (%ir-block.0): + liveins: $x0 + + ; CHECK-LABEL: name: i8_to_i64 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.ptr) + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 + ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] + ; CHECK: RET_ReallyLR implicit $x0 + %0:gpr(p0) = COPY $x0 + %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.ptr) + $x0 = COPY %2(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: i8_to_i32 +legalized: true +regBankSelected: true +body: | + bb.1 (%ir-block.0): + liveins: $x0 + + ; CHECK-LABEL: name: i8_to_i32 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.ptr) + ; CHECK: $w0 = COPY [[LDRBBui]] + ; CHECK: RET_ReallyLR implicit $w0 + %0:gpr(p0) = COPY $x0 + %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.ptr) + $w0 = COPY %2(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: i16_to_i32 +legalized: true +regBankSelected: true +body: | + bb.1 (%ir-block.0): + liveins: $x0 + + ; CHECK-LABEL: name: i16_to_i32 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.ptr) + ; CHECK: $w0 = COPY [[LDRHHui]] + ; CHECK: RET_ReallyLR implicit $w0 + %0:gpr(p0) = COPY $x0 + %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load 2 from %ir.ptr) + $w0 = COPY %2(s32) + RET_ReallyLR implicit $w0 + +... -- 2.40.0