From 16cbc63cb07d0f4b3385fb47d5f352de04f85c3f Mon Sep 17 00:00:00 2001 From: Chen Zheng Date: Wed, 30 Jan 2019 01:57:01 +0000 Subject: [PATCH] [PowerPC] more opportunity for converting reg+reg to reg+imm Differential Revision: https://reviews.llvm.org/D57314 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352583 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstrInfo.cpp | 4 ++-- .../PowerPC/convert-rr-to-ri-instr-add.mir | 17 +++++++++++++++++ 2 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index bb856c242ed..ecc5e28c0d8 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -3205,9 +3205,9 @@ bool PPCInstrInfo::isRegElgibleForForwarding(const MachineOperand &RegMO, } assert((&*It) == &DefMI && "DefMI is missing"); - // If DefMI also uses the register to be forwarded, we can only forward it + // If DefMI also defines the register to be forwarded, we can only forward it // if DefMI is being erased. - if (DefMI.readsRegister(Reg, &getRegisterInfo())) + if (DefMI.modifiesRegister(Reg, &getRegisterInfo())) return KillDefMI; return true; diff --git a/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir b/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir new file mode 100644 index 00000000000..420f1f58b68 --- /dev/null +++ b/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir @@ -0,0 +1,17 @@ +# RUN: llc -mtriple=powerpc64le--linux-gnu -stop-after ppc-pre-emit-peephole %s -o - -verify-machineinstrs | FileCheck %s + +--- +# ADDI8 + STFSX can be converted to ADDI8 + STFS even ADDI8 can not be erased. +name: testFwdOperandKilledAfter +# CHECK: name: testFwdOperandKilledAfter +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x3, $f1, $x5 + $x3 = ADDI8 $x5, 100 + STFSX killed $f1, $zero8, $x3 + ; CHECK: STFS killed $f1, 100, $x5 + STD killed $x3, killed $x5, 100 + ; CHECK: STD killed $x3, killed $x5, 100 + BLR8 implicit $lr8, implicit $rm +... -- 2.50.1