From 15e40f15261dfb3974a0742a3f9afe747d730bc2 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Mon, 21 Aug 2017 21:57:52 +0000
Subject: [PATCH] [InstCombine] add more tests for udiv/urem narrowing; NFC

We don't currently limit these folds with hasOneUse() or shouldChangeType().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311390 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../InstCombine/udivrem-change-width.ll       | 228 +++++++++++++-----
 1 file changed, 169 insertions(+), 59 deletions(-)

diff --git a/test/Transforms/InstCombine/udivrem-change-width.ll b/test/Transforms/InstCombine/udivrem-change-width.ll
index 1f59a4ac1f6..44824f3bb4f 100644
--- a/test/Transforms/InstCombine/udivrem-change-width.ll
+++ b/test/Transforms/InstCombine/udivrem-change-width.ll
@@ -1,6 +1,6 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target datalayout = "n8:32"
 
 ; PR4548
 define i8 @udiv_i8(i8 %a, i8 %b) {
@@ -15,6 +15,18 @@ define i8 @udiv_i8(i8 %a, i8 %b) {
   ret i8 %conv3
 }
 
+define <2 x i8> @udiv_i8_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @udiv_i8_vec(
+; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i8> %a, %b
+; CHECK-NEXT:    ret <2 x i8> [[DIV]]
+;
+  %za = zext <2 x i8> %a to <2 x i32>
+  %zb = zext <2 x i8> %b to <2 x i32>
+  %udiv = udiv <2 x i32> %za, %zb
+  %conv3 = trunc <2 x i32> %udiv to <2 x i8>
+  ret <2 x i8> %conv3
+}
+
 define i8 @urem_i8(i8 %a, i8 %b) {
 ; CHECK-LABEL: @urem_i8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, %b
@@ -27,6 +39,18 @@ define i8 @urem_i8(i8 %a, i8 %b) {
   ret i8 %conv3
 }
 
+define <2 x i8> @urem_i8_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @urem_i8_vec(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem <2 x i8> %a, %b
+; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
+;
+  %za = zext <2 x i8> %a to <2 x i32>
+  %zb = zext <2 x i8> %b to <2 x i32>
+  %udiv = urem <2 x i32> %za, %zb
+  %conv3 = trunc <2 x i32> %udiv to <2 x i8>
+  ret <2 x i8> %conv3
+}
+
 define i32 @udiv_i32(i8 %a, i8 %b) {
 ; CHECK-LABEL: @udiv_i32(
 ; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, %b
@@ -39,86 +63,111 @@ define i32 @udiv_i32(i8 %a, i8 %b) {
   ret i32 %udiv
 }
 
-define i32 @urem_i32(i8 %a, i8 %b) {
-; CHECK-LABEL: @urem_i32(
-; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, %b
-; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[TMP1]] to i32
-; CHECK-NEXT:    ret i32 [[UDIV]]
+define <2 x i32> @udiv_i32_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @udiv_i32_vec(
+; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i8> %a, %b
+; CHECK-NEXT:    [[UDIV:%.*]] = zext <2 x i8> [[DIV]] to <2 x i32>
+; CHECK-NEXT:    ret <2 x i32> [[UDIV]]
 ;
-  %za = zext i8 %a to i32
-  %zb = zext i8 %b to i32
-  %udiv = urem i32 %za, %zb
-  ret i32 %udiv
+  %za = zext <2 x i8> %a to <2 x i32>
+  %zb = zext <2 x i8> %b to <2 x i32>
+  %udiv = udiv <2 x i32> %za, %zb
+  ret <2 x i32> %udiv
 }
 
-define i32 @udiv_i32_c(i8 %a) {
-; CHECK-LABEL: @udiv_i32_c(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, 10
+define i32 @udiv_i32_multiuse(i8 %a, i8 %b) {
+; CHECK-LABEL: @udiv_i32_multiuse(
+; CHECK-NEXT:    [[ZA:%.*]] = zext i8 %a to i32
+; CHECK-NEXT:    [[ZB:%.*]] = zext i8 %b to i32
+; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, %b
 ; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[DIV]] to i32
-; CHECK-NEXT:    ret i32 [[UDIV]]
+; CHECK-NEXT:    [[EXTRA_USES:%.*]] = add nuw nsw i32 [[ZA]], [[ZB]]
+; CHECK-NEXT:    [[R:%.*]] = mul nuw nsw i32 [[EXTRA_USES]], [[UDIV]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %za = zext i8 %a to i32
-  %udiv = udiv i32 %za, 10
-  ret i32 %udiv
+  %zb = zext i8 %b to i32
+  %udiv = udiv i32 %za, %zb
+  %extra_uses = add i32 %za, %zb
+  %r = mul i32 %udiv, %extra_uses
+  ret i32 %r
 }
 
-define i32 @urem_i32_c(i8 %a) {
-; CHECK-LABEL: @urem_i32_c(
-; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, 10
-; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[TMP1]] to i32
+define i32 @udiv_illegal_type(i9 %a, i9 %b) {
+; CHECK-LABEL: @udiv_illegal_type(
+; CHECK-NEXT:    [[DIV:%.*]] = udiv i9 %a, %b
+; CHECK-NEXT:    [[UDIV:%.*]] = zext i9 [[DIV]] to i32
 ; CHECK-NEXT:    ret i32 [[UDIV]]
 ;
-  %za = zext i8 %a to i32
-  %udiv = urem i32 %za, 10
+  %za = zext i9 %a to i32
+  %zb = zext i9 %b to i32
+  %udiv = udiv i32 %za, %zb
   ret i32 %udiv
 }
 
-define <2 x i8> @udiv_i8_vec(<2 x i8> %a, <2 x i8> %b) {
-; CHECK-LABEL: @udiv_i8_vec(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i8> %a, %b
-; CHECK-NEXT:    ret <2 x i8> [[DIV]]
+define i32 @urem_i32(i8 %a, i8 %b) {
+; CHECK-LABEL: @urem_i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, %b
+; CHECK-NEXT:    [[UREM:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[UREM]]
 ;
-  %za = zext <2 x i8> %a to <2 x i32>
-  %zb = zext <2 x i8> %b to <2 x i32>
-  %udiv = udiv <2 x i32> %za, %zb
-  %conv3 = trunc <2 x i32> %udiv to <2 x i8>
-  ret <2 x i8> %conv3
+  %za = zext i8 %a to i32
+  %zb = zext i8 %b to i32
+  %urem = urem i32 %za, %zb
+  ret i32 %urem
 }
 
-define <2 x i8> @urem_i8_vec(<2 x i8> %a, <2 x i8> %b) {
-; CHECK-LABEL: @urem_i8_vec(
+define <2 x i32> @urem_i32_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @urem_i32_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = urem <2 x i8> %a, %b
-; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
+; CHECK-NEXT:    [[UREM:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
+; CHECK-NEXT:    ret <2 x i32> [[UREM]]
 ;
   %za = zext <2 x i8> %a to <2 x i32>
   %zb = zext <2 x i8> %b to <2 x i32>
-  %udiv = urem <2 x i32> %za, %zb
-  %conv3 = trunc <2 x i32> %udiv to <2 x i8>
-  ret <2 x i8> %conv3
+  %urem = urem <2 x i32> %za, %zb
+  ret <2 x i32> %urem
 }
 
-define <2 x i32> @udiv_i32_vec(<2 x i8> %a, <2 x i8> %b) {
-; CHECK-LABEL: @udiv_i32_vec(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i8> %a, %b
-; CHECK-NEXT:    [[UDIV:%.*]] = zext <2 x i8> [[DIV]] to <2 x i32>
-; CHECK-NEXT:    ret <2 x i32> [[UDIV]]
+define i32 @urem_i32_multiuse(i8 %a, i8 %b) {
+; CHECK-LABEL: @urem_i32_multiuse(
+; CHECK-NEXT:    [[ZA:%.*]] = zext i8 %a to i32
+; CHECK-NEXT:    [[ZB:%.*]] = zext i8 %b to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, %b
+; CHECK-NEXT:    [[UREM:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT:    [[EXTRA_USES:%.*]] = add nuw nsw i32 [[ZA]], [[ZB]]
+; CHECK-NEXT:    [[R:%.*]] = mul nuw nsw i32 [[EXTRA_USES]], [[UREM]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
-  %za = zext <2 x i8> %a to <2 x i32>
-  %zb = zext <2 x i8> %b to <2 x i32>
-  %udiv = udiv <2 x i32> %za, %zb
-  ret <2 x i32> %udiv
+  %za = zext i8 %a to i32
+  %zb = zext i8 %b to i32
+  %urem = urem i32 %za, %zb
+  %extra_uses = add i32 %za, %zb
+  %r = mul i32 %urem, %extra_uses
+  ret i32 %r
 }
 
-define <2 x i32> @urem_i32_vec(<2 x i8> %a, <2 x i8> %b) {
-; CHECK-LABEL: @urem_i32_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = urem <2 x i8> %a, %b
-; CHECK-NEXT:    [[UDIV:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
-; CHECK-NEXT:    ret <2 x i32> [[UDIV]]
+define i32 @urem_illegal_type(i9 %a, i9 %b) {
+; CHECK-LABEL: @urem_illegal_type(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i9 %a, %b
+; CHECK-NEXT:    [[UREM:%.*]] = zext i9 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[UREM]]
 ;
-  %za = zext <2 x i8> %a to <2 x i32>
-  %zb = zext <2 x i8> %b to <2 x i32>
-  %udiv = urem <2 x i32> %za, %zb
-  ret <2 x i32> %udiv
+  %za = zext i9 %a to i32
+  %zb = zext i9 %b to i32
+  %urem = urem i32 %za, %zb
+  ret i32 %urem
+}
+
+define i32 @udiv_i32_c(i8 %a) {
+; CHECK-LABEL: @udiv_i32_c(
+; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, 10
+; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[DIV]] to i32
+; CHECK-NEXT:    ret i32 [[UDIV]]
+;
+  %za = zext i8 %a to i32
+  %udiv = udiv i32 %za, 10
+  ret i32 %udiv
 }
 
 define <2 x i32> @udiv_i32_c_vec(<2 x i8> %a) {
@@ -132,14 +181,75 @@ define <2 x i32> @udiv_i32_c_vec(<2 x i8> %a) {
   ret <2 x i32> %udiv
 }
 
+define i32 @udiv_i32_c_multiuse(i8 %a) {
+; CHECK-LABEL: @udiv_i32_c_multiuse(
+; CHECK-NEXT:    [[ZA:%.*]] = zext i8 %a to i32
+; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, 10
+; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[DIV]] to i32
+; CHECK-NEXT:    [[EXTRA_USE:%.*]] = add nuw nsw i32 [[ZA]], [[UDIV]]
+; CHECK-NEXT:    ret i32 [[EXTRA_USE]]
+;
+  %za = zext i8 %a to i32
+  %udiv = udiv i32 %za, 10
+  %extra_use = add i32 %za, %udiv
+  ret i32 %extra_use
+}
+
+define i32 @udiv_illegal_type_c(i9 %a) {
+; CHECK-LABEL: @udiv_illegal_type_c(
+; CHECK-NEXT:    [[DIV:%.*]] = udiv i9 %a, 10
+; CHECK-NEXT:    [[UDIV:%.*]] = zext i9 [[DIV]] to i32
+; CHECK-NEXT:    ret i32 [[UDIV]]
+;
+  %za = zext i9 %a to i32
+  %udiv = udiv i32 %za, 10
+  ret i32 %udiv
+}
+
+define i32 @urem_i32_c(i8 %a) {
+; CHECK-LABEL: @urem_i32_c(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, 10
+; CHECK-NEXT:    [[UREM:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[UREM]]
+;
+  %za = zext i8 %a to i32
+  %urem = urem i32 %za, 10
+  ret i32 %urem
+}
+
 define <2 x i32> @urem_i32_c_vec(<2 x i8> %a) {
 ; CHECK-LABEL: @urem_i32_c_vec(
 ; CHECK-NEXT:    [[ZA:%.*]] = zext <2 x i8> %a to <2 x i32>
-; CHECK-NEXT:    [[UDIV:%.*]] = urem <2 x i32> [[ZA]], <i32 10, i32 17>
-; CHECK-NEXT:    ret <2 x i32> [[UDIV]]
+; CHECK-NEXT:    [[UREM:%.*]] = urem <2 x i32> [[ZA]], <i32 10, i32 17>
+; CHECK-NEXT:    ret <2 x i32> [[UREM]]
 ;
   %za = zext <2 x i8> %a to <2 x i32>
-  %udiv = urem <2 x i32> %za, <i32 10, i32 17>
-  ret <2 x i32> %udiv
+  %urem = urem <2 x i32> %za, <i32 10, i32 17>
+  ret <2 x i32> %urem
+}
+
+define i32 @urem_i32_c_multiuse(i8 %a) {
+; CHECK-LABEL: @urem_i32_c_multiuse(
+; CHECK-NEXT:    [[ZA:%.*]] = zext i8 %a to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, 10
+; CHECK-NEXT:    [[UREM:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT:    [[EXTRA_USE:%.*]] = add nuw nsw i32 [[ZA]], [[UREM]]
+; CHECK-NEXT:    ret i32 [[EXTRA_USE]]
+;
+  %za = zext i8 %a to i32
+  %urem = urem i32 %za, 10
+  %extra_use = add i32 %za, %urem
+  ret i32 %extra_use
+}
+
+define i32 @urem_illegal_type_c(i9 %a) {
+; CHECK-LABEL: @urem_illegal_type_c(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem i9 %a, 10
+; CHECK-NEXT:    [[UREM:%.*]] = zext i9 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[UREM]]
+;
+  %za = zext i9 %a to i32
+  %urem = urem i32 %za, 10
+  ret i32 %urem
 }
 
-- 
2.50.1