From 1338c14d0676434da021911c8824f00425d4895d Mon Sep 17 00:00:00 2001 From: Luke Cheeseman Date: Wed, 21 Aug 2019 09:09:56 +0000 Subject: [PATCH] [AArch64] Update MTE system register encodings The encodings for the system registers TFSRE0_EL1, TFSR_EL1 TFSR_EL2, TFSR_EL3 and TFSR_EL12 have been changed so that they consistently have CRn=5 and CRm=6 as per https://developer.arm.com/docs/ddi0487/latest. Differential Revision: https://reviews.llvm.org/D65442 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369505 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64SystemOperands.td | 10 ++--- test/MC/AArch64/armv8.5a-mte.s | 20 +++++----- test/MC/Disassembler/AArch64/armv8.5a-mte.txt | 40 +++++++++---------- 3 files changed, 35 insertions(+), 35 deletions(-) diff --git a/lib/Target/AArch64/AArch64SystemOperands.td b/lib/Target/AArch64/AArch64SystemOperands.td index 8ca031e3fee..da5a3a1e3b7 100644 --- a/lib/Target/AArch64/AArch64SystemOperands.td +++ b/lib/Target/AArch64/AArch64SystemOperands.td @@ -1452,11 +1452,11 @@ let Requires = [{ {AArch64::FeatureMTE} }] in { def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>; def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>; def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>; -def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0110, 0b0101, 0b000>; -def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0110, 0b0101, 0b000>; -def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0110, 0b0110, 0b000>; -def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0110, 0b0110, 0b000>; -def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0110, 0b0110, 0b001>; +def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b000>; +def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0101, 0b0110, 0b000>; +def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0101, 0b0110, 0b000>; +def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0101, 0b0110, 0b000>; +def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b001>; def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>; } // HasMTE diff --git a/test/MC/AArch64/armv8.5a-mte.s b/test/MC/AArch64/armv8.5a-mte.s index 98baa90a3c1..26076549b09 100644 --- a/test/MC/AArch64/armv8.5a-mte.s +++ b/test/MC/AArch64/armv8.5a-mte.s @@ -473,11 +473,11 @@ mrs x7, gmid_el1 // CHECK: mrs x0, TCO // encoding: [0xe0,0x42,0x3b,0xd5] // CHECK: mrs x1, GCR_EL1 // encoding: [0xc1,0x10,0x38,0xd5] // CHECK: mrs x2, RGSR_EL1 // encoding: [0xa2,0x10,0x38,0xd5] -// CHECK: mrs x3, TFSR_EL1 // encoding: [0x03,0x65,0x38,0xd5] -// CHECK: mrs x4, TFSR_EL2 // encoding: [0x04,0x65,0x3c,0xd5] -// CHECK: mrs x5, TFSR_EL3 // encoding: [0x05,0x66,0x3e,0xd5] -// CHECK: mrs x6, TFSR_EL12 // encoding: [0x06,0x66,0x3d,0xd5] -// CHECK: mrs x7, TFSRE0_EL1 // encoding: [0x27,0x66,0x38,0xd5] +// CHECK: mrs x3, TFSR_EL1 // encoding: [0x03,0x56,0x38,0xd5] +// CHECK: mrs x4, TFSR_EL2 // encoding: [0x04,0x56,0x3c,0xd5] +// CHECK: mrs x5, TFSR_EL3 // encoding: [0x05,0x56,0x3e,0xd5] +// CHECK: mrs x6, TFSR_EL12 // encoding: [0x06,0x56,0x3d,0xd5] +// CHECK: mrs x7, TFSRE0_EL1 // encoding: [0x27,0x56,0x38,0xd5] // CHECK: mrs x7, GMID_EL1 // encoding: [0x87,0x00,0x39,0xd5] // NOMTE: expected readable system register @@ -518,11 +518,11 @@ msr tfsre0_el1, x7 // CHECK: msr TCO, x0 // encoding: [0xe0,0x42,0x1b,0xd5] // CHECK: msr GCR_EL1, x1 // encoding: [0xc1,0x10,0x18,0xd5] // CHECK: msr RGSR_EL1, x2 // encoding: [0xa2,0x10,0x18,0xd5] -// CHECK: msr TFSR_EL1, x3 // encoding: [0x03,0x65,0x18,0xd5] -// CHECK: msr TFSR_EL2, x4 // encoding: [0x04,0x65,0x1c,0xd5] -// CHECK: msr TFSR_EL3, x5 // encoding: [0x05,0x66,0x1e,0xd5] -// CHECK: msr TFSR_EL12, x6 // encoding: [0x06,0x66,0x1d,0xd5] -// CHECK: msr TFSRE0_EL1, x7 // encoding: [0x27,0x66,0x18,0xd5] +// CHECK: msr TFSR_EL1, x3 // encoding: [0x03,0x56,0x18,0xd5] +// CHECK: msr TFSR_EL2, x4 // encoding: [0x04,0x56,0x1c,0xd5] +// CHECK: msr TFSR_EL3, x5 // encoding: [0x05,0x56,0x1e,0xd5] +// CHECK: msr TFSR_EL12, x6 // encoding: [0x06,0x56,0x1d,0xd5] +// CHECK: msr TFSRE0_EL1, x7 // encoding: [0x27,0x56,0x18,0xd5] // NOMTE: expected writable system register or pstate // NOMTE-NEXT: tco diff --git a/test/MC/Disassembler/AArch64/armv8.5a-mte.txt b/test/MC/Disassembler/AArch64/armv8.5a-mte.txt index c407797e5af..f93aae235ab 100644 --- a/test/MC/Disassembler/AArch64/armv8.5a-mte.txt +++ b/test/MC/Disassembler/AArch64/armv8.5a-mte.txt @@ -549,11 +549,11 @@ [0xe0,0x42,0x3b,0xd5] [0xc1,0x10,0x38,0xd5] [0xa2,0x10,0x38,0xd5] -[0x03,0x65,0x38,0xd5] -[0x04,0x65,0x3c,0xd5] -[0x05,0x66,0x3e,0xd5] -[0x06,0x66,0x3d,0xd5] -[0x27,0x66,0x38,0xd5] +[0x03,0x56,0x38,0xd5] +[0x04,0x56,0x3c,0xd5] +[0x05,0x56,0x3e,0xd5] +[0x06,0x56,0x3d,0xd5] +[0x27,0x56,0x38,0xd5] [0x88,0x00,0x39,0xd5] # CHECK: mrs x0, TCO @@ -569,11 +569,11 @@ # NOMTE: mrs x0, S3_3_C4_C2_7 # NOMTE: mrs x1, S3_0_C1_C0_6 # NOMTE: mrs x2, S3_0_C1_C0_5 -# NOMTE: mrs x3, S3_0_C6_C5_0 -# NOMTE: mrs x4, S3_4_C6_C5_0 -# NOMTE: mrs x5, S3_6_C6_C6_0 -# NOMTE: mrs x6, S3_5_C6_C6_0 -# NOMTE: mrs x7, S3_0_C6_C6_1 +# NOMTE: mrs x3, S3_0_C5_C6_0 +# NOMTE: mrs x4, S3_4_C5_C6_0 +# NOMTE: mrs x5, S3_6_C5_C6_0 +# NOMTE: mrs x6, S3_5_C5_C6_0 +# NOMTE: mrs x7, S3_0_C5_C6_1 # NOMTE: mrs x8, S3_1_C0_C0_4 [0x9f,0x40,0x03,0xd5] @@ -584,11 +584,11 @@ [0xe0,0x42,0x1b,0xd5] [0xc1,0x10,0x18,0xd5] [0xa2,0x10,0x18,0xd5] -[0x03,0x65,0x18,0xd5] -[0x04,0x65,0x1c,0xd5] -[0x05,0x66,0x1e,0xd5] -[0x06,0x66,0x1d,0xd5] -[0x27,0x66,0x18,0xd5] +[0x03,0x56,0x18,0xd5] +[0x04,0x56,0x1c,0xd5] +[0x05,0x56,0x1e,0xd5] +[0x06,0x56,0x1d,0xd5] +[0x27,0x56,0x18,0xd5] [0x88,0x00,0x19,0xd5] # CHECK: msr TCO, x0 @@ -605,9 +605,9 @@ # NOMTE: msr S3_3_C4_C2_7, x0 # NOMTE: msr S3_0_C1_C0_6, x1 # NOMTE: msr S3_0_C1_C0_5, x2 -# NOMTE: msr S3_0_C6_C5_0, x3 -# NOMTE: msr S3_4_C6_C5_0, x4 -# NOMTE: msr S3_6_C6_C6_0, x5 -# NOMTE: msr S3_5_C6_C6_0, x6 -# NOMTE: msr S3_0_C6_C6_1, x7 +# NOMTE: msr S3_0_C5_C6_0, x3 +# NOMTE: msr S3_4_C5_C6_0, x4 +# NOMTE: msr S3_6_C5_C6_0, x5 +# NOMTE: msr S3_5_C5_C6_0, x6 +# NOMTE: msr S3_0_C5_C6_1, x7 # NOMTE: msr S3_1_C0_C0_4, x8 -- 2.40.0