From 11e5e3bbe1bdb925b7df1204bd4e68a014a96f12 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 16 Jun 2016 00:56:47 +0000 Subject: [PATCH] AMDGPU: Disable scheduling in some slow tests Disabling the pre-RA scheduler on large-work-group-registers causes it to be ~50% slower. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272860 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AMDGPU/large-work-group-registers.ll | 2 +- test/CodeGen/AMDGPU/spill-scavenge-offset.ll | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/test/CodeGen/AMDGPU/large-work-group-registers.ll b/test/CodeGen/AMDGPU/large-work-group-registers.ll index b49078565b7..468633da56d 100644 --- a/test/CodeGen/AMDGPU/large-work-group-registers.ll +++ b/test/CodeGen/AMDGPU/large-work-group-registers.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tonga -post-RA-scheduler=0 < %s | FileCheck %s ; CHECK: NumVgprs: 64 define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, <3 x i32> inreg, <3 x i32> inreg, <3 x i32>) #0 { diff --git a/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/test/CodeGen/AMDGPU/spill-scavenge-offset.ll index 7b51d75c678..9b3dfab2be6 100644 --- a/test/CodeGen/AMDGPU/spill-scavenge-offset.ll +++ b/test/CodeGen/AMDGPU/spill-scavenge-offset.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s -; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga < %s | FileCheck %s -; +; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s +; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s + ; ; There is something about Tonga that causes this test to spend a lot of time ; in the default register allocator. -- 2.50.1