From 11e1f0b5096ca6c9eb14b8d15c642ec41602bdfe Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard@arm.com>
Date: Fri, 1 Feb 2019 09:23:51 +0000
Subject: [PATCH] [CodeGen] Don't scavenge non-saved regs in exception throwing
 functions

Previously, LiveRegUnits was assuming that if a block has no successors
and does not return, then no registers are live at the end of it
(because the end of the block is unreachable). This was causing the
register scavenger to use callee-saved registers to materialise stack
frame addresses without saving them in the prologue. This would normally
be fine, because the end of the block is unreachable, but this is not
legal if the block ends by throwing a C++ exception. If this happens,
the scratch register will be modified, but its previous value won't be
preserved, so it doesn't get restored by the exception unwinder.

Differential revision: https://reviews.llvm.org/D57381



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352844 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/LiveRegUnits.cpp                  | 16 ++++---
 .../ARM/register-scavenger-exceptions.mir     | 47 +++++++++++++++++++
 2 files changed, 56 insertions(+), 7 deletions(-)
 create mode 100644 test/CodeGen/ARM/register-scavenger-exceptions.mir

diff --git a/lib/CodeGen/LiveRegUnits.cpp b/lib/CodeGen/LiveRegUnits.cpp
index c58a06a6974..6afb7fb7aa1 100644
--- a/lib/CodeGen/LiveRegUnits.cpp
+++ b/lib/CodeGen/LiveRegUnits.cpp
@@ -125,13 +125,15 @@ void LiveRegUnits::addPristines(const MachineFunction &MF) {
 
 void LiveRegUnits::addLiveOuts(const MachineBasicBlock &MBB) {
   const MachineFunction &MF = *MBB.getParent();
-  if (!MBB.succ_empty()) {
-    addPristines(MF);
-    // To get the live-outs we simply merge the live-ins of all successors.
-    for (const MachineBasicBlock *Succ : MBB.successors())
-      addBlockLiveIns(*this, *Succ);
-  } else if (MBB.isReturnBlock()) {
-    // For the return block: Add all callee saved registers.
+
+  addPristines(MF);
+
+  // To get the live-outs we simply merge the live-ins of all successors.
+  for (const MachineBasicBlock *Succ : MBB.successors())
+    addBlockLiveIns(*this, *Succ);
+
+  // For the return block: Add all callee saved registers.
+  if (MBB.isReturnBlock()) {
     const MachineFrameInfo &MFI = MF.getFrameInfo();
     if (MFI.isCalleeSavedInfoValid())
       addCalleeSavedRegs(*this, MF);
diff --git a/test/CodeGen/ARM/register-scavenger-exceptions.mir b/test/CodeGen/ARM/register-scavenger-exceptions.mir
new file mode 100644
index 00000000000..58f6cd77557
--- /dev/null
+++ b/test/CodeGen/ARM/register-scavenger-exceptions.mir
@@ -0,0 +1,47 @@
+# RUN: llc -o - %s -run-pass=prologepilog | FileCheck %s
+
+--- |
+  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "armv7--none-eabi"
+
+  define hidden void @_Z3foov(i32 %P0, ...) {
+  entry:
+    %V1 = alloca [4075 x i8], align 8
+    %tmp3 = alloca i8, i32 undef, align 8
+    unreachable
+  }
+
+  declare dso_local void @_Z3barv() noreturn
+
+...
+---
+# Check that the register scavenger does pick r5 (not preserved in prolog) for
+# materialising a stack frame address when the function ends in throwing an
+# exception.
+# CHECK: $sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r10, killed $r11, killed $lr
+# CHECK-NOT: $r5
+name:            _Z3foov
+stack:
+  - { id: 0, name: V1, type: default, offset: 0, size: 5000, alignment: 8,
+      stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -4080, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+  - { id: 1, name: tmp3, type: variable-sized, offset: 0, alignment: 1,
+      stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -4112, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.0.entry:
+
+    $r0 = MOVi 0, 14, $noreg, $noreg
+    $r1 = MOVi 0, 14, $noreg, $noreg
+    $r2 = MOVi 0, 14, $noreg, $noreg
+    $r3 = MOVi 0, 14, $noreg, $noreg
+    $r4 = MOVi 0, 14, $noreg, $noreg
+    STRi12 killed $lr, %stack.2, 0, 14, $noreg :: (store 4 into %stack.2)
+    BL @_Z3barv, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3, implicit killed $r4, implicit-def $sp
+
+...
-- 
2.40.0