From 11283fb2c8458150697e07d68d20ae7fe94325b5 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 14 Sep 2017 20:54:29 +0000 Subject: [PATCH] AMDGPU: Fix violating constant bus restriction You can't use madmk/madmk if it already uses an SGPR input. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313298 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIInstrInfo.cpp | 9 +++++---- test/CodeGen/AMDGPU/twoaddr-mad.mir | 22 ++++++++++++++++++++++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index e60124e75a9..de0eb8b7427 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2150,9 +2150,8 @@ static int64_t getFoldableImm(const MachineOperand* MO) { const MachineFunction *MF = MO->getParent()->getParent()->getParent(); const MachineRegisterInfo &MRI = MF->getRegInfo(); auto Def = MRI.getUniqueVRegDef(MO->getReg()); - if (Def && (Def->getOpcode() == AMDGPU::S_MOV_B32 || - Def->getOpcode() == AMDGPU::V_MOV_B32_e32) && - Def->getOperand(1).isImm()) + if (Def && Def->getOpcode() == AMDGPU::V_MOV_B32_e32 && + Def->getOperand(1).isImm()) return Def->getOperand(1).getImm(); return AMDGPU::NoRegister; } @@ -2194,7 +2193,9 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB, const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp); const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod); - if (!Src0Mods && !Src1Mods && !Clamp && !Omod) { + if (!Src0Mods && !Src1Mods && !Clamp && !Omod && + // If we have an SGPR input, we will violate the constant bus restriction. + !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg())) { if (auto Imm = getFoldableImm(Src2)) { return BuildMI(*MBB, MI, MI.getDebugLoc(), get(IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32)) diff --git a/test/CodeGen/AMDGPU/twoaddr-mad.mir b/test/CodeGen/AMDGPU/twoaddr-mad.mir index ebda1d26ddc..cd8931fb21a 100644 --- a/test/CodeGen/AMDGPU/twoaddr-mad.mir +++ b/test/CodeGen/AMDGPU/twoaddr-mad.mir @@ -108,3 +108,25 @@ body: | %1 = V_MOV_B32_e32 1078523331, implicit %exec %2 = V_MAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit %exec ... + +# Make sure constant bus restriction isn't violated if src0 is an SGPR. + +# GCN-LABEL: name: test_madak_sgpr_src0_f32 +# GCN: %1 = V_MOV_B32_e32 1078523331, implicit %exec +# GCN: %2 = V_MAD_F32 0, killed %0, 0, %1, 0, %3, 0, 0, implicit %exec + +--- +name: test_madak_sgpr_src0_f32 +registers: + - { id: 0, class: sreg_32_xm0 } + - { id: 1, class: vgpr_32} + - { id: 2, class: vgpr_32 } + - { id: 3, class: vgpr_32 } +body: | + bb.0: + + %0 = IMPLICIT_DEF + %1 = V_MOV_B32_e32 1078523331, implicit %exec + %2 = V_MAC_F32_e32 killed %0, %1, %3, implicit %exec + +... -- 2.50.1