From 0e78a271fdb25c794b1b24a86b6d92d87ec69186 Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Wed, 29 May 2019 08:40:33 +0000 Subject: [PATCH] [AArch64][SVE2] Asm: support SVE2 Floating Point Pairwise Group Summary: Patch adds support for the following instructions: SVE2 floating-point pairwise operations: * FADDP, FMAXNMP, FMINNMP, FMAXP, FMINP The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62383 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361933 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64SVEInstrInfo.td | 7 +++ lib/Target/AArch64/SVEInstrFormats.td | 33 ++++++++++++++ test/MC/AArch64/SVE2/faddp-diagnostics.s | 50 ++++++++++++++++++++ test/MC/AArch64/SVE2/faddp.s | 53 ++++++++++++++++++++++ test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s | 50 ++++++++++++++++++++ test/MC/AArch64/SVE2/fmaxnmp.s | 53 ++++++++++++++++++++++ test/MC/AArch64/SVE2/fmaxp-diagnostics.s | 50 ++++++++++++++++++++ test/MC/AArch64/SVE2/fmaxp.s | 53 ++++++++++++++++++++++ test/MC/AArch64/SVE2/fminnmp-diagnostics.s | 50 ++++++++++++++++++++ test/MC/AArch64/SVE2/fminnmp.s | 53 ++++++++++++++++++++++ test/MC/AArch64/SVE2/fminp-diagnostics.s | 50 ++++++++++++++++++++ test/MC/AArch64/SVE2/fminp.s | 53 ++++++++++++++++++++++ 12 files changed, 555 insertions(+) create mode 100644 test/MC/AArch64/SVE2/faddp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/faddp.s create mode 100644 test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/fmaxnmp.s create mode 100644 test/MC/AArch64/SVE2/fmaxp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/fmaxp.s create mode 100644 test/MC/AArch64/SVE2/fminnmp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/fminnmp.s create mode 100644 test/MC/AArch64/SVE2/fminp-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/fminp.s diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index 4095c6d9582..2d8b9a9879f 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1294,6 +1294,13 @@ let Predicates = [HasSVE2] in { defm FCVTNT_ZPmZ : sve2_fp_convert_down_narrow<"fcvtnt">; defm FCVTLT_ZPmZ : sve2_fp_convert_up_long<"fcvtlt">; + // SVE2 floating-point pairwise operations + defm FADDP_ZPmZZ : sve2_fp_pairwise_pred<0b000, "faddp">; + defm FMAXNMP_ZPmZZ : sve2_fp_pairwise_pred<0b100, "fmaxnmp">; + defm FMINNMP_ZPmZZ : sve2_fp_pairwise_pred<0b101, "fminnmp">; + defm FMAXP_ZPmZZ : sve2_fp_pairwise_pred<0b110, "fmaxp">; + defm FMINP_ZPmZZ : sve2_fp_pairwise_pred<0b111, "fminp">; + // Predicated shifts defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index 699c21d867b..967e0a41794 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -1472,6 +1472,39 @@ multiclass sve2_fp_convert_down_odd_rounding { def _DtoS : sve2_fp_convert_precision<0b0010, asm, ZPR32, ZPR64>; } +//===----------------------------------------------------------------------===// +// SVE2 Floating Point Pairwise Group +//===----------------------------------------------------------------------===// + +class sve2_fp_pairwise_pred sz, bits<3> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), + asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zm; + bits<5> Zdn; + let Inst{31-24} = 0b01100100; + let Inst{23-22} = sz; + let Inst{21-19} = 0b010; + let Inst{18-16} = opc; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; + let DestructiveInstType = Destructive; + let ElementSize = zprty.ElementSize; +} + +multiclass sve2_fp_pairwise_pred opc, string asm> { + def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>; + def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>; + def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>; +} + //===----------------------------------------------------------------------===// // SVE Stack Allocation Group //===----------------------------------------------------------------------===// diff --git a/test/MC/AArch64/SVE2/faddp-diagnostics.s b/test/MC/AArch64/SVE2/faddp-diagnostics.s new file mode 100644 index 00000000000..99d4f5eefe4 --- /dev/null +++ b/test/MC/AArch64/SVE2/faddp-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +faddp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: faddp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +faddp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: faddp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +faddp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: faddp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +faddp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: faddp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +faddp z0.h, p0/z, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: faddp z0.h, p0/z, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +faddp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: faddp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/faddp.s b/test/MC/AArch64/SVE2/faddp.s new file mode 100644 index 00000000000..8c05eff4cc1 --- /dev/null +++ b/test/MC/AArch64/SVE2/faddp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +faddp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: faddp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x50,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 50 64 + +faddp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: faddp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x90,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 90 64 + +faddp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d0 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +faddp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: faddp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd0,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d0 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +faddp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d0 64 diff --git a/test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s b/test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s new file mode 100644 index 00000000000..2d51333416a --- /dev/null +++ b/test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +fmaxnmp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: fmaxnmp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +fmaxnmp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxnmp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +fmaxnmp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxnmp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmaxnmp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxnmp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fmaxnmp z0.h, p0/z, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmaxnmp z0.h, p0/z, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fmaxnmp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fmaxnmp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/fmaxnmp.s b/test/MC/AArch64/SVE2/fmaxnmp.s new file mode 100644 index 00000000000..6a35174a498 --- /dev/null +++ b/test/MC/AArch64/SVE2/fmaxnmp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fmaxnmp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: fmaxnmp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x54,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 54 64 + +fmaxnmp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: fmaxnmp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x94,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 94 64 + +fmaxnmp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d4 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +fmaxnmp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: fmaxnmp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd4,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d4 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +fmaxnmp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d4 64 diff --git a/test/MC/AArch64/SVE2/fmaxp-diagnostics.s b/test/MC/AArch64/SVE2/fmaxp-diagnostics.s new file mode 100644 index 00000000000..6165e74878b --- /dev/null +++ b/test/MC/AArch64/SVE2/fmaxp-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +fmaxp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: fmaxp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +fmaxp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +fmaxp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmaxp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fmaxp z0.h, p0/z, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmaxp z0.h, p0/z, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fmaxp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fmaxp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/fmaxp.s b/test/MC/AArch64/SVE2/fmaxp.s new file mode 100644 index 00000000000..9d2eb4c2f38 --- /dev/null +++ b/test/MC/AArch64/SVE2/fmaxp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fmaxp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: fmaxp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x56,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 56 64 + +fmaxp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: fmaxp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x96,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 96 64 + +fmaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d6 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +fmaxp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: fmaxp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd6,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d6 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +fmaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d6 64 diff --git a/test/MC/AArch64/SVE2/fminnmp-diagnostics.s b/test/MC/AArch64/SVE2/fminnmp-diagnostics.s new file mode 100644 index 00000000000..2338816d06d --- /dev/null +++ b/test/MC/AArch64/SVE2/fminnmp-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +fminnmp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: fminnmp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +fminnmp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminnmp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +fminnmp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminnmp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fminnmp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminnmp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fminnmp z0.h, p0/z, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fminnmp z0.h, p0/z, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fminnmp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fminnmp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/fminnmp.s b/test/MC/AArch64/SVE2/fminnmp.s new file mode 100644 index 00000000000..b40510a0645 --- /dev/null +++ b/test/MC/AArch64/SVE2/fminnmp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fminnmp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: fminnmp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x55,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 55 64 + +fminnmp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: fminnmp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x95,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 95 64 + +fminnmp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d5 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +fminnmp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: fminnmp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd5,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d5 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +fminnmp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d5 64 diff --git a/test/MC/AArch64/SVE2/fminp-diagnostics.s b/test/MC/AArch64/SVE2/fminp-diagnostics.s new file mode 100644 index 00000000000..cc55a2652fb --- /dev/null +++ b/test/MC/AArch64/SVE2/fminp-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +fminp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: fminp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +fminp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +fminp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fminp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fminp z0.h, p0/z, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fminp z0.h, p0/z, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fminp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fminp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/fminp.s b/test/MC/AArch64/SVE2/fminp.s new file mode 100644 index 00000000000..f33ad1b0e58 --- /dev/null +++ b/test/MC/AArch64/SVE2/fminp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fminp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: fminp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x57,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 57 64 + +fminp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: fminp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x97,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 97 64 + +fminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d7 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +fminp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: fminp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d7 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +fminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d7 64 -- 2.50.1