From 0e7879be673c21afe9629400c32eab93e37bbf2c Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 13 Feb 2019 07:42:31 +0000 Subject: [PATCH] [X86] Refactor the FP_TO_INTHelper interface. NFCI -Pull the final stack load creation from the two callers into the helper. -Return a single SDValue instead of a std::pair. -Remove the Replace flag which isn't really needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353920 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 103 +++++++++++------------------ lib/Target/X86/X86ISelLowering.h | 4 +- 2 files changed, 38 insertions(+), 69 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index f461dd3dd87..2fb01f60d67 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -18070,9 +18070,9 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, // Otherwise we lower it to a sequence ending with a FIST, return a // pair, and the caller is responsible for loading // the final integer result from StackSlot. -std::pair +SDValue X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, - bool IsSigned, bool IsReplace) const { + bool IsSigned) const { SDLoc DL(Op); EVT DstTy = Op.getValueType(); @@ -18082,7 +18082,7 @@ X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) { // f16 must be promoted before using the lowering in this routine. // fp128 does not use this lowering. - return std::make_pair(SDValue(), SDValue()); + return SDValue(); } // If using FIST to compute an unsigned i64, we'll need some fixup @@ -18106,9 +18106,9 @@ X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, // These are really Legal. if (DstTy == MVT::i32 && isScalarFPTypeInSSEReg(TheVT)) - return std::make_pair(SDValue(), SDValue()); + return SDValue(); if (Subtarget.is64Bit() && DstTy == MVT::i64 && isScalarFPTypeInSSEReg(TheVT)) - return std::make_pair(SDValue(), SDValue()); + return SDValue(); // We lower FP->int64 into FISTP64 followed by a load from a temporary // stack slot. @@ -18117,8 +18117,6 @@ X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, int SSFI = MF.getFrameInfo().CreateStackObject(MemSize, MemSize, false); SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); - const unsigned Opc = X86ISD::FP_TO_INT_IN_MEM; - SDValue Chain = DAG.getEntryNode(); SDValue Value = Op.getOperand(0); SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment. @@ -18190,51 +18188,41 @@ X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, StackSlot = DAG.getFrameIndex(SSFI, PtrVT); } + // Build the FP_TO_INT*_IN_MEM MachineMemOperand *MMO = MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI), MachineMemOperand::MOStore, MemSize, MemSize); + SDValue Ops[] = { Chain, Value, StackSlot }; + SDValue FIST = DAG.getMemIntrinsicNode(X86ISD::FP_TO_INT_IN_MEM, DL, + DAG.getVTList(MVT::Other), + Ops, DstTy, MMO); - if (UnsignedFixup) { - - // Insert the FIST, load its result as two i32's, - // and XOR the high i32 with Adjust. + if (!UnsignedFixup) + return DAG.getLoad(Op.getValueType(), SDLoc(Op), FIST, StackSlot, + MachinePointerInfo()); - SDValue FistOps[] = { Chain, Value, StackSlot }; - SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), - FistOps, DstTy, MMO); + // Insert the FIST, load its result as two i32's, + // and XOR the high i32 with Adjust. - SDValue Low32 = - DAG.getLoad(MVT::i32, DL, FIST, StackSlot, MachinePointerInfo()); - SDValue HighAddr = DAG.getMemBasePlusOffset(StackSlot, 4, DL); + SDValue Low32 = + DAG.getLoad(MVT::i32, DL, FIST, StackSlot, MachinePointerInfo()); + SDValue HighAddr = DAG.getMemBasePlusOffset(StackSlot, 4, DL); - SDValue High32 = - DAG.getLoad(MVT::i32, DL, FIST, HighAddr, MachinePointerInfo()); - High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust); + SDValue High32 = + DAG.getLoad(MVT::i32, DL, FIST, HighAddr, MachinePointerInfo()); + High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust); - if (Subtarget.is64Bit()) { - // Join High32 and Low32 into a 64-bit result. - // (High32 << 32) | Low32 - Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32); - High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32); - High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32, - DAG.getConstant(32, DL, MVT::i8)); - SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32); - return std::make_pair(Result, SDValue()); - } - - SDValue ResultOps[] = { Low32, High32 }; - - SDValue pair = IsReplace - ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps) - : DAG.getMergeValues(ResultOps, DL); - return std::make_pair(pair, SDValue()); - } else { - // Build the FP_TO_INT*_IN_MEM - SDValue Ops[] = { Chain, Value, StackSlot }; - SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), - Ops, DstTy, MMO); - return std::make_pair(FIST, StackSlot); + if (Subtarget.is64Bit()) { + // Join High32 and Low32 into a 64-bit result. + // (High32 << 32) | Low32 + Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32); + High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32); + High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32, + DAG.getConstant(32, DL, MVT::i8)); + return DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32); } + + return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, { Low32, High32 }); } static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG, @@ -18744,19 +18732,11 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const { assert(!VT.isVector()); - std::pair Vals = FP_TO_INTHelper(Op, DAG, - IsSigned, /*IsReplace=*/ false); - SDValue FIST = Vals.first, StackSlot = Vals.second; - // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. - if (!FIST.getNode()) - return Op; - - if (StackSlot.getNode()) - // Load the result. - return DAG.getLoad(VT, SDLoc(Op), FIST, StackSlot, MachinePointerInfo()); + if (SDValue V = FP_TO_INTHelper(Op, DAG, IsSigned)) + return V; - // The node is the result. - return FIST; + // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. + return Op; } static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) { @@ -27020,17 +27000,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, return; } - std::pair Vals = - FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); - SDValue FIST = Vals.first, StackSlot = Vals.second; - if (FIST.getNode()) { - // Return a load from the stack slot. - if (StackSlot.getNode()) - Results.push_back( - DAG.getLoad(VT, dl, FIST, StackSlot, MachinePointerInfo())); - else - Results.push_back(FIST); - } + if (SDValue V = FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned)) + Results.push_back(V); return; } case ISD::SINT_TO_FP: { diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index c22fb9306c2..45d73085259 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -1229,9 +1229,7 @@ namespace llvm { unsigned getAddressSpace(void) const; - std::pair FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, - bool isSigned, - bool isReplace) const; + SDValue FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool isSigned) const; SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const; -- 2.40.0