From 0cb06771b3baac694f383df387bd3e8562382570 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Tue, 24 Jul 2018 12:19:01 +0000 Subject: [PATCH] [x86/SLH] Tidy up a comment, using doxygen structure and wording it to be more accurate and understandable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337822 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86SpeculativeLoadHardening.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/lib/Target/X86/X86SpeculativeLoadHardening.cpp index c2453cef496..10e1132d877 100644 --- a/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -1866,11 +1866,13 @@ bool X86SpeculativeLoadHardeningPass::canHardenRegister(unsigned Reg) { return RC->hasSuperClassEq(GPRRegClasses[Log2_32(RegBytes)]); } -// We can harden non-leaking loads into register without touching the address -// by just hiding all of the loaded bits. We use an `or` instruction to do -// this because having the poison value be all ones allows us to use the same -// value below. And the goal is just for the loaded bits to not be exposed to -// execution and coercing them to one is sufficient. +/// Harden a load by hardening the loaded value in the defined register. +/// +/// We can harden a non-leaking load into a register without touching the +/// address by just hiding all of the loaded bits during misspeculation. We use +/// an `or` instruction to do this because we set up our poison value as all +/// ones. And the goal is just for the loaded bits to not be exposed to +/// execution and coercing them to one is sufficient. void X86SpeculativeLoadHardeningPass::hardenPostLoad(MachineInstr &MI) { MachineBasicBlock &MBB = *MI.getParent(); DebugLoc Loc = MI.getDebugLoc(); -- 2.50.1