From 0c5071f56198367ea2b29f8e34ddb9ecd1773985 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Mon, 18 Aug 2014 17:55:41 +0000 Subject: [PATCH] [X86][Haswell][SchedModel] Add architecture specific scheduling models. Group: Integer MMX and XMM instructions. Sub-group: Logic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215916 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86SchedHaswell.td | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td index 5b72b319f1e..38833de7c25 100644 --- a/lib/Target/X86/X86SchedHaswell.td +++ b/lib/Target/X86/X86SchedHaswell.td @@ -1505,4 +1505,35 @@ def WritePMULLDm : SchedWriteRes<[HWPort0, HWPort23]> { } def : InstRW<[WritePMULLDm, ReadAfterLd], (instregex "(V?)PMULLD(Y?)rm")>; +//-- Logic instructions --// + +// PTEST. +// v,v. +def WritePTESTr : SchedWriteRes<[HWPort0, HWPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1, 1]; +} +def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rr")>; + +// v,m. +def WritePTESTm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [1, 1, 1]; +} +def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rm")>; + +// PSLL,PSRL,PSRA W/D/Q. +// x,x / v,v,x. +def WritePShift : SchedWriteRes<[HWPort0, HWPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1, 1]; +} +def : InstRW<[WritePShift], (instregex "(V?)PS(LL|RL|RA)(W|D|Q)(Y?)rr")>; + +// PSLL,PSRL DQ. +def : InstRW<[WriteP5], (instregex "(V?)PS(R|L)LDQ(Y?)ri")>; + } // SchedModel -- 2.40.0