From 0aad2c18f1e5269e6eaebf617bceb611fa6208af Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Wed, 19 Nov 2014 23:20:35 +0000 Subject: [PATCH] Revert "[Reassociate] Update test cases due to r222142." This reverts commit r222144. Commit r222142 is being reverted due to a spec2006/gcc execution-time regression. Update mips-varargs test as well. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@222397 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/aarch64-neon-intrinsics.c | 4 ++-- test/CodeGen/bmi-builtins.c | 8 ++++---- test/CodeGen/builtins-arm-exclusive.c | 8 ++++---- test/CodeGen/mips-varargs.c | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/test/CodeGen/aarch64-neon-intrinsics.c b/test/CodeGen/aarch64-neon-intrinsics.c index 31ac8474b3..b120779590 100644 --- a/test/CodeGen/aarch64-neon-intrinsics.c +++ b/test/CodeGen/aarch64-neon-intrinsics.c @@ -8172,13 +8172,13 @@ int64_t test_vcltzd_s64(int64_t a) { int64_t test_vtstd_s64(int64_t a, int64_t b) { // CHECK-LABEL: test_vtstd_s64 -// CHECK: {{cmtst d[0-9]+, d[0-9]+, d[0-9]+|tst x0, x1}} +// CHECK: {{cmtst d[0-9]+, d[0-9]+, d[0-9]+|tst x1, x0}} return (int64_t)vtstd_s64(a, b); } uint64_t test_vtstd_u64(uint64_t a, uint64_t b) { // CHECK-LABEL: test_vtstd_u64 -// CHECK: {{cmtst d[0-9]+, d[0-9]+, d[0-9]+|tst x0, x1}} +// CHECK: {{cmtst d[0-9]+, d[0-9]+, d[0-9]+|tst x1, x0}} return (uint64_t)vtstd_u64(a, b); } diff --git a/test/CodeGen/bmi-builtins.c b/test/CodeGen/bmi-builtins.c index 6a5923917e..92332e3a12 100644 --- a/test/CodeGen/bmi-builtins.c +++ b/test/CodeGen/bmi-builtins.c @@ -20,7 +20,7 @@ unsigned short test__tzcnt_u16(unsigned short __X) { unsigned int test__andn_u32(unsigned int __X, unsigned int __Y) { // CHECK: [[DEST:%.*]] = xor i32 %{{.*}}, -1 - // CHECK-NEXT: %{{.*}} = and i32 [[DEST]], %{{.*}} + // CHECK-NEXT: %{{.*}} = and i32 %{{.*}}, [[DEST]] return __andn_u32(__X, __Y); } @@ -54,7 +54,7 @@ unsigned int test__tzcnt_u32(unsigned int __X) { unsigned long long test__andn_u64(unsigned long __X, unsigned long __Y) { // CHECK: [[DEST:%.*]] = xor i64 %{{.*}}, -1 - // CHECK-NEXT: %{{.*}} = and i64 [[DEST]], %{{.*}} + // CHECK-NEXT: %{{.*}} = and i64 %{{.*}}, [[DEST]] return __andn_u64(__X, __Y); } @@ -95,7 +95,7 @@ unsigned short test_tzcnt_u16(unsigned short __X) { unsigned int test_andn_u32(unsigned int __X, unsigned int __Y) { // CHECK: [[DEST:%.*]] = xor i32 %{{.*}}, -1 - // CHECK-NEXT: %{{.*}} = and i32 [[DEST]], %{{.*}} + // CHECK-NEXT: %{{.*}} = and i32 %{{.*}}, [[DEST]] return _andn_u32(__X, __Y); } @@ -130,7 +130,7 @@ unsigned int test_tzcnt_u32(unsigned int __X) { unsigned long long test_andn_u64(unsigned long __X, unsigned long __Y) { // CHECK: [[DEST:%.*]] = xor i64 %{{.*}}, -1 - // CHECK-NEXT: %{{.*}} = and i64 [[DEST]], %{{.*}} + // CHECK-NEXT: %{{.*}} = and i64 %{{.*}}, [[DEST]] return _andn_u64(__X, __Y); } diff --git a/test/CodeGen/builtins-arm-exclusive.c b/test/CodeGen/builtins-arm-exclusive.c index e2df429e3d..2b10238c0f 100644 --- a/test/CodeGen/builtins-arm-exclusive.c +++ b/test/CodeGen/builtins-arm-exclusive.c @@ -94,7 +94,7 @@ int test_ldrex(char *addr, long long *addr64, float *addrfloat) { // CHECK: [[RESHI64:%.*]] = zext i32 [[RESHI]] to i64 // CHECK: [[RESLO64:%.*]] = zext i32 [[RESLO]] to i64 // CHECK: [[RESHIHI:%.*]] = shl nuw i64 [[RESHI64]], 32 -// CHECK: [[INTRES:%.*]] = or i64 [[RESLO64]], [[RESHIHI]] +// CHECK: [[INTRES:%.*]] = or i64 [[RESHIHI]], [[RESLO64]] // CHECK: bitcast i64 [[INTRES]] to double // CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i64(i64* [[ADDR64]]) @@ -178,7 +178,7 @@ int test_ldaex(char *addr, long long *addr64, float *addrfloat) { // CHECK: [[RESHI64:%.*]] = zext i32 [[RESHI]] to i64 // CHECK: [[RESLO64:%.*]] = zext i32 [[RESLO]] to i64 // CHECK: [[RESHIHI:%.*]] = shl nuw i64 [[RESHI64]], 32 -// CHECK: [[INTRES:%.*]] = or i64 [[RESLO64]], [[RESHIHI]] +// CHECK: [[INTRES:%.*]] = or i64 [[RESHIHI]], [[RESLO64]] // CHECK: bitcast i64 [[INTRES]] to double // CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldaxr.p0i64(i64* [[ADDR64]]) @@ -323,7 +323,7 @@ __int128 test_ldrex_128(__int128 *addr) { // CHECK-ARM64: [[RESHI64:%.*]] = zext i64 [[RESHI]] to i128 // CHECK-ARM64: [[RESLO64:%.*]] = zext i64 [[RESLO]] to i128 // CHECK-ARM64: [[RESHIHI:%.*]] = shl nuw i128 [[RESHI64]], 64 -// CHECK-ARM64: [[INTRES:%.*]] = or i128 [[RESLO64]], [[RESHIHI]] +// CHECK-ARM64: [[INTRES:%.*]] = or i128 [[RESHIHI]], [[RESLO64]] // CHECK-ARM64: ret i128 [[INTRES]] } @@ -349,7 +349,7 @@ __int128 test_ldaex_128(__int128 *addr) { // CHECK-ARM64: [[RESHI64:%.*]] = zext i64 [[RESHI]] to i128 // CHECK-ARM64: [[RESLO64:%.*]] = zext i64 [[RESLO]] to i128 // CHECK-ARM64: [[RESHIHI:%.*]] = shl nuw i128 [[RESHI64]], 64 -// CHECK-ARM64: [[INTRES:%.*]] = or i128 [[RESLO64]], [[RESHIHI]] +// CHECK-ARM64: [[INTRES:%.*]] = or i128 [[RESHIHI]], [[RESLO64]] // CHECK-ARM64: ret i128 [[INTRES]] } diff --git a/test/CodeGen/mips-varargs.c b/test/CodeGen/mips-varargs.c index f8f2bff43e..e8b6e29002 100644 --- a/test/CodeGen/mips-varargs.c +++ b/test/CodeGen/mips-varargs.c @@ -98,7 +98,7 @@ int test_i32_2args(char *fmt, ...) { // NEW: [[ARG2:%.+]] = trunc i64 [[TMP4]] to i32 // // ALL: call void @llvm.va_end(i8* [[VA1]]) -// ALL: [[ADD:%.+]] = add nsw i32 [[ARG1]], [[ARG2]] +// ALL: [[ADD:%.+]] = add nsw i32 [[ARG2]], [[ARG1]] // ALL: ret i32 [[ADD]] // ALL: } -- 2.40.0