From 0a21c3c2992a3b0181deadc6c73b04483d463852 Mon Sep 17 00:00:00 2001 From: Marek Olsak Date: Wed, 24 May 2017 14:53:50 +0000 Subject: [PATCH] Revert "AMDGPU: Fold CI-specific complex SMRD patterns into existing complex patterns" This reverts commit e065977c4b5f68ab845400b256f6a3822b1325fa. It doesn't work. S_LOAD_DWORD_IMM_ci and friends aren't selected by any of the patterns, so it was putting 32-bit literals into the 8-bit field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303754 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 36 ++++++++++++++-------- lib/Target/AMDGPU/AMDGPUSubtarget.h | 4 --- lib/Target/AMDGPU/SMInstructions.td | 27 +++++++++++++++- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 2 +- 4 files changed, 51 insertions(+), 18 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 5eb2324c79c..19fce064783 100644 --- a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -145,8 +145,10 @@ private: bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset, bool &Imm) const; bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const; + bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const; bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const; bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const; + bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const; bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const; bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const; @@ -1328,6 +1330,7 @@ bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode, return false; SDLoc SL(ByteOffsetNode); + AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration(); int64_t ByteOffset = C->getSExtValue(); int64_t EncodedOffset = AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset); @@ -1340,8 +1343,8 @@ bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode, if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset)) return false; - if (Subtarget->has32BitLiteralSMRDOffset() && - ByteOffset % 4 == 0 && isUInt<32>(EncodedOffset)) { + if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) { + // 32-bit Immediates are supported on Sea Islands. Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32); } else { SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32); @@ -1373,15 +1376,20 @@ bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase, bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const { bool Imm; + return SelectSMRD(Addr, SBase, Offset, Imm) && Imm; +} - if (!SelectSMRD(Addr, SBase, Offset, Imm)) +bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase, + SDValue &Offset) const { + + if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS) return false; - if (Subtarget->has32BitLiteralSMRDOffset() && - isa(Offset)) - return true; + bool Imm; + if (!SelectSMRD(Addr, SBase, Offset, Imm)) + return false; - return Imm; + return !Imm && isa(Offset); } bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase, @@ -1394,15 +1402,19 @@ bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase, bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const { bool Imm; + return SelectSMRDOffset(Addr, Offset, Imm) && Imm; +} - if (!SelectSMRDOffset(Addr, Offset, Imm)) +bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr, + SDValue &Offset) const { + if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS) return false; - if (Subtarget->has32BitLiteralSMRDOffset() && - isa(Offset)) - return true; + bool Imm; + if (!SelectSMRDOffset(Addr, Offset, Imm)) + return false; - return Imm; + return !Imm && isa(Offset); } bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr, diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.h b/lib/Target/AMDGPU/AMDGPUSubtarget.h index 24ebde5dc93..66087942681 100644 --- a/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -399,10 +399,6 @@ public: return FlatScratchInsts; } - bool has32BitLiteralSMRDOffset() const { - return getGeneration() == SEA_ISLANDS; - } - bool isMesaKernel(const MachineFunction &MF) const { return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv()); } diff --git a/lib/Target/AMDGPU/SMInstructions.td b/lib/Target/AMDGPU/SMInstructions.td index 828fd009eeb..5b840a14dbc 100644 --- a/lib/Target/AMDGPU/SMInstructions.td +++ b/lib/Target/AMDGPU/SMInstructions.td @@ -234,8 +234,10 @@ def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ }]>; def SMRDImm : ComplexPattern; +def SMRDImm32 : ComplexPattern; def SMRDSgpr : ComplexPattern; def SMRDBufferImm : ComplexPattern; +def SMRDBufferImm32 : ComplexPattern; def SMRDBufferSgpr : ComplexPattern; let Predicates = [isGCN] in { @@ -274,7 +276,7 @@ defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>; defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>; // 1. Offset as an immediate -def : Pat < +def SM_LOAD_PATTERN : Pat < // name this pattern to reuse AddedComplexity on CI (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)), (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset, 0) >; @@ -502,3 +504,26 @@ class SMRD_Real_ci op, SM_Pseudo ps> } def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>; + +let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity in { + +class SMRD_Pattern_ci : Pat < + (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), + (vt (!cast(Instr#"_IMM_ci") $sbase, $offset, 0))> { + let Predicates = [isCIOnly]; +} + +def : SMRD_Pattern_ci <"S_LOAD_DWORD", i32>; +def : SMRD_Pattern_ci <"S_LOAD_DWORDX2", v2i32>; +def : SMRD_Pattern_ci <"S_LOAD_DWORDX4", v4i32>; +def : SMRD_Pattern_ci <"S_LOAD_DWORDX8", v8i32>; +def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>; + +def : Pat < + (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)), + (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset, 0)> { + let Predicates = [isCI]; // should this be isCIOnly? +} + +} // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity + diff --git a/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index e14587e413a..630f469eabf 100644 --- a/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -763,7 +763,7 @@ int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) { bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) { int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset); - return isSI(ST) || isCI(ST) ? ByteOffset % 4 == 0 && isUInt<8>(EncodedOffset) : + return isSI(ST) || isCI(ST) ? isUInt<8>(EncodedOffset) : isUInt<20>(EncodedOffset); } } // end namespace AMDGPU -- 2.40.0