From 0906927bc751624d560a93598def6d057e3c51c7 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Fri, 11 Nov 2016 14:10:12 +0000 Subject: [PATCH] [AArch64] Enable merging of adjacent zero stores for all subtargets. This optimization merges adjacent zero stores into a wider store. e.g., strh wzr, [x0] strh wzr, [x0, #2] ; becomes str wzr, [x0] e.g., str wzr, [x0] str wzr, [x0, #4] ; becomes str xzr, [x0] Previously, this was only enabled for Kryo and Cortex-A57. Differential Revision: https://reviews.llvm.org/D26396 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286592 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64.td | 7 ------- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp | 3 +-- lib/Target/AArch64/AArch64Subtarget.h | 2 -- test/CodeGen/AArch64/arm64-narrow-st-merge.ll | 4 +--- 4 files changed, 2 insertions(+), 14 deletions(-) diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td index 5e658272de8..b7f473f358b 100644 --- a/lib/Target/AArch64/AArch64.td +++ b/lib/Target/AArch64/AArch64.td @@ -61,11 +61,6 @@ def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true", "Reserve X18, making it unavailable " "as a GPR">; -def FeatureMergeNarrowZeroSt : SubtargetFeature<"merge-narrow-zero-st", - "MergeNarrowZeroStores", "true", - "Merge narrow zero store " - "instructions">; - def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", "Use alias analysis during codegen">; @@ -182,7 +177,6 @@ def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", FeatureCrypto, FeatureCustomCheapAsMoveHandling, FeatureFPARMv8, - FeatureMergeNarrowZeroSt, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, @@ -253,7 +247,6 @@ def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", FeatureCrypto, FeatureCustomCheapAsMoveHandling, FeatureFPARMv8, - FeatureMergeNarrowZeroSt, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index 3fe589fe7f3..fc5ed6e9c8c 100644 --- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -1699,8 +1699,7 @@ bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { UsedRegs.resize(TRI->getNumRegs()); bool Modified = false; - bool enableNarrowZeroStOpt = - Subtarget->mergeNarrowStores() && !Subtarget->requiresStrictAlign(); + bool enableNarrowZeroStOpt = !Subtarget->requiresStrictAlign(); for (auto &MBB : Fn) Modified |= optimizeBlock(MBB, enableNarrowZeroStOpt); diff --git a/lib/Target/AArch64/AArch64Subtarget.h b/lib/Target/AArch64/AArch64Subtarget.h index 359e68904b1..e053d0d70fb 100644 --- a/lib/Target/AArch64/AArch64Subtarget.h +++ b/lib/Target/AArch64/AArch64Subtarget.h @@ -71,7 +71,6 @@ protected: // StrictAlign - Disallow unaligned memory accesses. bool StrictAlign = false; - bool MergeNarrowZeroStores = false; bool UseAA = false; bool PredictableSelectIsExpensive = false; bool BalanceFPOps = false; @@ -179,7 +178,6 @@ public: bool hasCrypto() const { return HasCrypto; } bool hasCRC() const { return HasCRC; } bool hasRAS() const { return HasRAS; } - bool mergeNarrowStores() const { return MergeNarrowZeroStores; } bool balanceFPOps() const { return BalanceFPOps; } bool predictableSelectIsExpensive() const { return PredictableSelectIsExpensive; diff --git a/test/CodeGen/AArch64/arm64-narrow-st-merge.ll b/test/CodeGen/AArch64/arm64-narrow-st-merge.ll index 5800dfce587..4158bcc11e6 100644 --- a/test/CodeGen/AArch64/arm64-narrow-st-merge.ll +++ b/test/CodeGen/AArch64/arm64-narrow-st-merge.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple aarch64_be--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=kryo -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple aarch64--none-eabi -verify-machineinstrs | FileCheck %s ; CHECK-LABEL: Strh_zero ; CHECK: str wzr -- 2.50.1