From 08f0ec731b8b0f89bc646f3028b799ab49272a74 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 18 Jun 2019 18:22:30 +0000 Subject: [PATCH] [TargetLowering] SimplifyDemandedBits - Cleanup ANY_EXTEND handling Match SIGN_EXTEND + ZERO_EXTEND handling - will be adding ANY_EXTEND_VECTOR_INREG support in a future patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363716 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f8dbeb44fa0..dcd8478e48b 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1440,12 +1440,18 @@ bool TargetLowering::SimplifyDemandedBits( break; } case ISD::ANY_EXTEND: { + // TODO: Add ISD::ANY_EXTEND_VECTOR_INREG support. SDValue Src = Op.getOperand(0); - unsigned InBits = Src.getScalarValueSizeInBits(); + EVT SrcVT = Src.getValueType(); + unsigned InBits = SrcVT.getScalarSizeInBits(); + unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; APInt InDemandedBits = DemandedBits.trunc(InBits); - if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth + 1)) + APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); + if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, + Depth + 1)) return true; assert(!Known.hasConflict() && "Bits known to be one AND zero?"); + assert(Known.getBitWidth() == InBits && "Src width has changed?"); Known = Known.zext(BitWidth, false /* => any extend */); break; } -- 2.40.0