From 0855745b7b0f2c9a53ac3e927960a76925a100d8 Mon Sep 17 00:00:00 2001 From: Jessica Paquette Date: Sat, 9 Feb 2019 00:37:31 +0000 Subject: [PATCH] Recommit "[GlobalISel] Introduce a generic floating point floor opcode, G_FFLOOR"" After r353586, we won't fail on the AMDGPU floor pattern that was killing the importer before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353589 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Support/TargetOpcodes.def | 3 +++ include/llvm/Target/GenericOpcodes.td | 7 +++++++ include/llvm/Target/GlobalISel/SelectionDAGCompat.td | 1 + .../AArch64/GlobalISel/legalizer-info-validation.mir | 5 ++++- 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/llvm/Support/TargetOpcodes.def b/include/llvm/Support/TargetOpcodes.def index f44f0f131a9..70a2128bd85 100644 --- a/include/llvm/Support/TargetOpcodes.def +++ b/include/llvm/Support/TargetOpcodes.def @@ -530,6 +530,9 @@ HANDLE_TARGET_OPCODE(G_FSIN) /// Floating point square root. HANDLE_TARGET_OPCODE(G_FSQRT) +/// Floating point floor. +HANDLE_TARGET_OPCODE(G_FFLOOR) + /// Generic AddressSpaceCast. HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) diff --git a/include/llvm/Target/GenericOpcodes.td b/include/llvm/Target/GenericOpcodes.td index b61ed926501..41d1ed9937a 100644 --- a/include/llvm/Target/GenericOpcodes.td +++ b/include/llvm/Target/GenericOpcodes.td @@ -579,6 +579,13 @@ def G_FSQRT : GenericInstruction { let hasSideEffects = 0; } +// Floating point floor of a value. +def G_FFLOOR : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + //------------------------------------------------------------------------------ // Opcodes for LLVM Intrinsics //------------------------------------------------------------------------------ diff --git a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index cbda4ab86a5..6b0434a0758 100644 --- a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -93,6 +93,7 @@ def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; +def : GINodeEquiv; // Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some // complications that tablegen must take care of. For example, Predicates such diff --git a/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index 09574f0b85d..ab144eedfac 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -340,7 +340,10 @@ # DEBUG: .. the first uncovered type index: 1, OK # # DEBUG-NEXT: G_FSQRT (opcode {{[0-9]+}}): 1 type index -# DEBUG: .. the first uncovered type index: 1, OK +# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_FFLOOR (opcode {{[0-9]+}}): 1 type index +# DEBUG: .. type index coverage check SKIPPED: no rules defined # CHECK-NOT: ill-defined -- 2.40.0