From 079481adb815dfb086020e4594fe9776780bb778 Mon Sep 17 00:00:00 2001
From: Tim Northover <tnorthover@apple.com>
Date: Fri, 28 Jul 2017 17:11:01 +0000
Subject: [PATCH] GlobalISel: map 128-bit values to an FPR by default.

Eventually we may want to allow a pair of GPRs but absolutely nothing in the
entire world is ready for that yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309404 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../AArch64/AArch64RegisterBankInfo.cpp       |  3 ++-
 .../AArch64/GlobalISel/arm64-fallback.ll      | 18 ----------------
 test/CodeGen/AArch64/reg-bank-128bit.mir      | 21 +++++++++++++++++++
 3 files changed, 23 insertions(+), 19 deletions(-)
 create mode 100644 test/CodeGen/AArch64/reg-bank-128bit.mir

diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index 69124dbd0f8..69f3ff6cc8c 100644
--- a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -488,7 +488,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 
     // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
     // For floating-point instructions, scalars go in FPRs.
-    if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
+    if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc) ||
+        Ty.getSizeInBits() > 64)
       OpRegBankIdx[Idx] = PMI_FirstFPR;
     else
       OpRegBankIdx[Idx] = PMI_FirstGPR;
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index 48f500eb36b..11fa721fc64 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -79,24 +79,6 @@ define void @odd_vector(<7 x i32>* %addr) {
   ret void
 }
 
-  ; RegBankSelect crashed when given invalid mappings, and AArch64's
-  ; implementation produce valid-but-nonsense mappings for G_SEQUENCE.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
-; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_mapping
-; FALLBACK-WITH-REPORT-OUT-LABEL: sequence_mapping:
-define void @sequence_mapping([2 x i64] %in) {
-  ret void
-}
-
-  ; Legalizer was asserting when it enountered an unexpected default action.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
-; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for legal_default
-; FALLBACK-WITH-REPORT-LABEL: legal_default:
-define void @legal_default([8 x i8] %in) {
-  insertvalue { [4 x i8], [8 x i8], [4 x i8] } undef, [8 x i8] %in, 1
-  ret void
-}
-
   ; AArch64 was asserting instead of returning an invalid mapping for unknown
   ; sizes.
 ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: ret: '  ret i128 undef' (in function: sequence_sizes)
diff --git a/test/CodeGen/AArch64/reg-bank-128bit.mir b/test/CodeGen/AArch64/reg-bank-128bit.mir
new file mode 100644
index 00000000000..6ea651d38c5
--- /dev/null
+++ b/test/CodeGen/AArch64/reg-bank-128bit.mir
@@ -0,0 +1,21 @@
+# RUN: llc -mtriple=aarch64 -global-isel -run-pass=regbankselect -o - %s | FileCheck %s
+---
+name:            test_large_merge
+legalized:       true
+registers:
+body: |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2
+
+    ; CHECK-LABEL: name: test_large_merge
+    ; CHECK: registers:
+    ; CHECK:       - { id: 0, class: gpr
+    ; CHECK:       - { id: 1, class: gpr
+    ; CHECK:       - { id: 2, class: gpr
+    ; CHECK:       - { id: 3, class: fpr
+    %0:_(s64) = COPY %x0
+    %1:_(s64) = COPY %x1
+    %2:_(p0) = COPY %x2
+    %3:_(s128) = G_MERGE_VALUES %0, %1
+    %d0 = COPY %3
+...
-- 
2.50.1