From 0782e893a9946ee3012d3d1a5ad9eaf12ea07db1 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 27 Nov 2017 14:39:50 +0000 Subject: [PATCH] [X86] Add INVLPGA to the existing INVLPG scheduling git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319031 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrSVM.td | 7 ++++--- test/CodeGen/X86/schedule-x86_64.ll | 20 ++++++++++---------- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/lib/Target/X86/X86InstrSVM.td b/lib/Target/X86/X86InstrSVM.td index c847be7ec09..41867099a6c 100644 --- a/lib/Target/X86/X86InstrSVM.td +++ b/lib/Target/X86/X86InstrSVM.td @@ -52,11 +52,12 @@ let Uses = [RAX] in def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>; +let SchedRW = [WriteSystem] in { // 0F 01 DF let Uses = [EAX, ECX] in def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins), - "invlpga\t{%ecx, %eax|eax, ecx}", []>, TB, Requires<[Not64BitMode]>; + "invlpga\t{%ecx, %eax|eax, ecx}", [], IIC_INVLPG>, TB, Requires<[Not64BitMode]>; let Uses = [RAX, ECX] in def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins), - "invlpga\t{%ecx, %rax|rax, ecx}", []>, TB, Requires<[In64BitMode]>; - + "invlpga\t{%ecx, %rax|rax, ecx}", [], IIC_INVLPG>, TB, Requires<[In64BitMode]>; +} // SchedRW diff --git a/test/CodeGen/X86/schedule-x86_64.ll b/test/CodeGen/X86/schedule-x86_64.ll index e99359be1ac..cdc06d72ca8 100644 --- a/test/CodeGen/X86/schedule-x86_64.ll +++ b/test/CodeGen/X86/schedule-x86_64.ll @@ -1077,7 +1077,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; GENERIC: # BB#0: ; GENERIC-NEXT: #APP ; GENERIC-NEXT: invlpg (%rdi) # sched: [100:0.33] -; GENERIC-NEXT: invlpga %ecx, %rax +; GENERIC-NEXT: invlpga %ecx, %rax # sched: [100:0.33] ; GENERIC-NEXT: #NO_APP ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -1085,7 +1085,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; ATOM: # BB#0: ; ATOM-NEXT: #APP ; ATOM-NEXT: invlpg (%rdi) # sched: [71:35.50] -; ATOM-NEXT: invlpga %ecx, %rax +; ATOM-NEXT: invlpga %ecx, %rax # sched: [71:35.50] ; ATOM-NEXT: #NO_APP ; ATOM-NEXT: retq # sched: [79:39.50] ; @@ -1093,7 +1093,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; SLM: # BB#0: ; SLM-NEXT: #APP ; SLM-NEXT: invlpg (%rdi) # sched: [100:1.00] -; SLM-NEXT: invlpga %ecx, %rax +; SLM-NEXT: invlpga %ecx, %rax # sched: [100:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] ; @@ -1101,7 +1101,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; SANDY: # BB#0: ; SANDY-NEXT: #APP ; SANDY-NEXT: invlpg (%rdi) # sched: [100:0.33] -; SANDY-NEXT: invlpga %ecx, %rax +; SANDY-NEXT: invlpga %ecx, %rax # sched: [100:0.33] ; SANDY-NEXT: #NO_APP ; SANDY-NEXT: retq # sched: [1:1.00] ; @@ -1109,7 +1109,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; HASWELL: # BB#0: ; HASWELL-NEXT: #APP ; HASWELL-NEXT: invlpg (%rdi) # sched: [100:0.25] -; HASWELL-NEXT: invlpga %ecx, %rax +; HASWELL-NEXT: invlpga %ecx, %rax # sched: [100:0.25] ; HASWELL-NEXT: #NO_APP ; HASWELL-NEXT: retq # sched: [2:1.00] ; @@ -1117,7 +1117,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; BROADWELL: # BB#0: ; BROADWELL-NEXT: #APP ; BROADWELL-NEXT: invlpg (%rdi) # sched: [100:0.25] -; BROADWELL-NEXT: invlpga %ecx, %rax +; BROADWELL-NEXT: invlpga %ecx, %rax # sched: [100:0.25] ; BROADWELL-NEXT: #NO_APP ; BROADWELL-NEXT: retq # sched: [7:1.00] ; @@ -1125,7 +1125,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; SKYLAKE: # BB#0: ; SKYLAKE-NEXT: #APP ; SKYLAKE-NEXT: invlpg (%rdi) # sched: [100:0.25] -; SKYLAKE-NEXT: invlpga %ecx, %rax +; SKYLAKE-NEXT: invlpga %ecx, %rax # sched: [100:0.25] ; SKYLAKE-NEXT: #NO_APP ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; @@ -1133,7 +1133,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; SKX: # BB#0: ; SKX-NEXT: #APP ; SKX-NEXT: invlpg (%rdi) # sched: [100:0.25] -; SKX-NEXT: invlpga %ecx, %rax +; SKX-NEXT: invlpga %ecx, %rax # sched: [100:0.25] ; SKX-NEXT: #NO_APP ; SKX-NEXT: retq # sched: [7:1.00] ; @@ -1141,7 +1141,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; BTVER2: # BB#0: ; BTVER2-NEXT: #APP ; BTVER2-NEXT: invlpg (%rdi) # sched: [100:0.17] -; BTVER2-NEXT: invlpga %ecx, %rax +; BTVER2-NEXT: invlpga %ecx, %rax # sched: [100:0.17] ; BTVER2-NEXT: #NO_APP ; BTVER2-NEXT: retq # sched: [4:1.00] ; @@ -1149,7 +1149,7 @@ define void @test_invlpg_invlpga(i8 *%a0) optsize { ; ZNVER1: # BB#0: ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: invlpg (%rdi) # sched: [100:?] -; ZNVER1-NEXT: invlpga %ecx, %rax +; ZNVER1-NEXT: invlpga %ecx, %rax # sched: [100:?] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] tail call void asm sideeffect "invlpg $0 \0A\09 invlpga %ecx, %rax", "*m"(i8 *%a0) nounwind -- 2.50.1