From 0773a82c471dfd418b306fbf97cd37f25484cfff Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Wed, 21 Jun 2017 19:21:30 +0000
Subject: [PATCH] [Hexagon] Handle more types of immediate operands in
 expand-condsets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305943 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Hexagon/HexagonExpandCondsets.cpp | 15 +++++++++++--
 test/CodeGen/Hexagon/expand-condsets-imm.mir | 22 ++++++++++++++++++++
 2 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 test/CodeGen/Hexagon/expand-condsets-imm.mir

diff --git a/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 9f8c9ded812..734f3c6658d 100644
--- a/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -567,8 +567,19 @@ unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
     }
     llvm_unreachable("Invalid register operand");
   }
-  if (SO.isImm() || SO.isFPImm())
-    return IfTrue ? C2_cmoveit : C2_cmoveif;
+  switch (SO.getType()) {
+    case MachineOperand::MO_Immediate:
+    case MachineOperand::MO_FPImmediate:
+    case MachineOperand::MO_ConstantPoolIndex:
+    case MachineOperand::MO_TargetIndex:
+    case MachineOperand::MO_JumpTableIndex:
+    case MachineOperand::MO_ExternalSymbol:
+    case MachineOperand::MO_GlobalAddress:
+    case MachineOperand::MO_BlockAddress:
+      return IfTrue ? C2_cmoveit : C2_cmoveif;
+    default:
+      break;
+  }
   llvm_unreachable("Unexpected source operand");
 }
 
diff --git a/test/CodeGen/Hexagon/expand-condsets-imm.mir b/test/CodeGen/Hexagon/expand-condsets-imm.mir
new file mode 100644
index 00000000000..1b0988393b7
--- /dev/null
+++ b/test/CodeGen/Hexagon/expand-condsets-imm.mir
@@ -0,0 +1,22 @@
+# RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s
+# Check that we can expand a mux with a global as an immediate operand.
+# CHECK: C2_cmoveif undef %0, @G
+
+--- |
+  @G = global i32 0, align 4
+  define void @fred() { ret void }
+...
+---
+name: fred
+tracksRegLiveness: true
+
+registers:
+  - { id: 0, class: predregs }
+  - { id: 1, class: intregs }
+body: |
+  bb.1:
+    %1 = IMPLICIT_DEF
+    %1 = C2_muxir undef %0, %1, @G
+    %r0 = COPY %1
+...
+
-- 
2.50.1