From 0555b650347d62914067a03ed0cf4d8bb9241d44 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 6 Apr 2017 04:04:10 +0000 Subject: [PATCH] Revert accidental commit of r299619. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299622 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 46 ++++++++++++++------- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 86a558f3624..d3ccdcd5ffd 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -569,6 +569,37 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, } return false; // Don't fall through, will infinitely loop. case ISD::AND: + // If the RHS is a constant, check to see if the LHS would be zero without + // using the bits from the RHS. Below, we use knowledge about the RHS to + // simplify the LHS, here we're using information from the LHS to simplify + // the RHS. + if (ConstantSDNode *RHSC = dyn_cast(Op.getOperand(1))) { + SDValue Op0 = Op.getOperand(0); + APInt LHSZero, LHSOne; + // Do not increment Depth here; that can cause an infinite loop. + TLO.DAG.computeKnownBits(Op0, LHSZero, LHSOne, Depth); + // If the LHS already has zeros where RHSC does, this and is dead. + if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) + return TLO.CombineTo(Op, Op0); + + // If any of the set bits in the RHS are known zero on the LHS, shrink + // the constant. + if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) + return true; + + // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its + // constant, but if this 'and' is only clearing bits that were just set by + // the xor, then this 'and' can be eliminated by shrinking the mask of + // the xor. For example, for a 32-bit X: + // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1 + if (isBitwiseNot(Op0) && Op0.hasOneUse() && + LHSOne == ~RHSC->getAPIntValue()) { + SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, Op.getValueType(), + Op0.getOperand(0), Op.getOperand(1)); + return TLO.CombineTo(Op, Xor); + } + } + if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, KnownOne, TLO, Depth+1)) return true; @@ -594,21 +625,6 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) return true; - if (ConstantSDNode *RHSC = dyn_cast(Op.getOperand(1))) { - SDValue Op0 = Op.getOperand(0); - // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its - // constant, but if this 'and' is only clearing bits that were just set by - // the xor, then this 'and' can be eliminated by shrinking the mask of - // the xor. For example, for a 32-bit X: - // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1 - if (isBitwiseNot(Op0) && Op0.hasOneUse() && - KnownOne2 == ~RHSC->getAPIntValue()) { - SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, Op.getValueType(), - Op0.getOperand(0), Op.getOperand(1)); - return TLO.CombineTo(Op, Xor); - } - } - // Output known-1 bits are only known if set in both the LHS & RHS. KnownOne &= KnownOne2; // Output known-0 are known to be clear if zero in either the LHS | RHS. -- 2.50.1