From 04b36a711b6b8d07cc42d677a68d65067dada654 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 13 Mar 2017 05:47:56 +0000 Subject: [PATCH] [AVX-512] Add EVEX2VEX test cases for the cvt instructions fixed in r297599 and r297600. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297603 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/evex-to-vex-compress.mir | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/test/CodeGen/X86/evex-to-vex-compress.mir b/test/CodeGen/X86/evex-to-vex-compress.mir index 138cd540cce..2295ddb5b2b 100755 --- a/test/CodeGen/X86/evex-to-vex-compress.mir +++ b/test/CodeGen/X86/evex-to-vex-compress.mir @@ -2130,8 +2130,12 @@ body: | %edi = VCVTSD2SIZrr %xmm0 ; CHECK: %xmm0 = VCVTSD2SSrm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSD2SSZrm %xmm0, %rdi, 1, _, 0, _ + ; CHECK: %xmm0 = Int_VCVTSD2SSrm %xmm0, %rdi, 1, _, 0, _ + %xmm0 = VCVTSD2SSZrm_Int %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VCVTSD2SSrr %xmm0, _ %xmm0 = VCVTSD2SSZrr %xmm0, _ + ; CHECK: %xmm0 = Int_VCVTSD2SSrr %xmm0, _ + %xmm0 = VCVTSD2SSZrr_Int %xmm0, _ ; CHECK: %xmm0 = VCVTSI2SDrm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSI2SDZrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = Int_VCVTSI2SDrm %xmm0, %rdi, 1, _, 0, _ @@ -2166,10 +2170,18 @@ body: | %xmm0 = VCVTSI642SSZrr_Int %xmm0, _ ; CHECK: %xmm0 = VCVTSS2SDrm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSS2SDZrm %xmm0, %rdi, 1, _, 0, _ + ; CHECK: %xmm0 = Int_VCVTSS2SDrm %xmm0, %rdi, 1, _, 0, _ + %xmm0 = VCVTSS2SDZrm_Int %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VCVTSS2SDrr %xmm0, _ %xmm0 = VCVTSS2SDZrr %xmm0, _ + ; CHECK: %xmm0 = Int_VCVTSS2SDrr %xmm0, _ + %xmm0 = VCVTSS2SDZrr_Int %xmm0, _ + ; CHECK: %rdi = VCVTSS2SI64rm %rdi, %xmm0, 1, _, 0 + %rdi = VCVTSS2SI64Zrm %rdi, %xmm0, 1, _, 0 ; CHECK: %rdi = VCVTSS2SI64rr %xmm0 %rdi = VCVTSS2SI64Zrr %xmm0 + ; CHECK: %edi = VCVTSS2SIrm %rdi, %xmm0, 1, _, 0 + %edi = VCVTSS2SIZrm %rdi, %xmm0, 1, _, 0 ; CHECK: %edi = VCVTSS2SIrr %xmm0 %edi = VCVTSS2SIZrr %xmm0 ; CHECK: %rdi = VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0 @@ -4438,8 +4450,12 @@ body: | %edi = VCVTSD2SIZrr %xmm16 ; CHECK: %xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, _, 0, _ + ; CHECK: %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, _, 0, _ + %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSD2SSZrr %xmm16, _ %xmm16 = VCVTSD2SSZrr %xmm16, _ + ; CHECK: %xmm16 = VCVTSD2SSZrr_Int %xmm16, _ + %xmm16 = VCVTSD2SSZrr_Int %xmm16, _ ; CHECK: %xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSI2SDZrm_Int %xmm16, %rdi, 1, _, 0, _ @@ -4474,8 +4490,12 @@ body: | %xmm16 = VCVTSI642SSZrr_Int %xmm16, _ ; CHECK: %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _ + ; CHECK: %xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, _, 0, _ + %xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSS2SDZrr %xmm16, _ %xmm16 = VCVTSS2SDZrr %xmm16, _ + ; CHECK: %xmm16 = VCVTSS2SDZrr_Int %xmm16, _ + %xmm16 = VCVTSS2SDZrr_Int %xmm16, _ ; CHECK: %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, _, 0 %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, _, 0 ; CHECK: %rdi = VCVTSS2SI64Zrr %xmm16 -- 2.50.1