From 03e1ccdf9df1766525d21486883e9a2e92713bee Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Sat, 4 Jun 2016 03:43:06 +0000 Subject: [PATCH] Merging r268287: ------------------------------------------------------------------------ r268287 | thomas.stellard | 2016-05-02 12:37:56 -0700 (Mon, 02 May 2016) | 19 lines AMDGPU/SI: Set the kill flag on temp VGPRs used to restore SGPRs from scratch Summary: When we restore an SGPR value from scratch, we first load it into a temporary VGPR and then use v_readlane_b32 to copy the value from the VGPR back into an SGPR. We weren't setting the kill flag on the VGPR in the v_readlane_b32 instruction, so the register scavenger wasn't able to re-use this temp value later. I wasn't able to create a lit test for this. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19744 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271770 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp index 5a88fea91f5..eb4ba7585a3 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -411,7 +411,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, .addMemOperand(MMO); BuildMI(*MBB, MI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg) - .addReg(TmpReg) + .addReg(TmpReg, RegState::Kill) .addImm(0) .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); } -- 2.50.1