From 02b0ff16a7325ca1e58288fec08dfcf710e6039c Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 29 Jul 2019 09:49:23 +0000 Subject: [PATCH] [SystemZ] Regenerate <8 x i31> store test To help show the diffs from an upcoming SimplifyDemandedBits patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367216 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../SystemZ/store_nonbytesized_vecs.ll | 65 ++++++++++--------- 1 file changed, 33 insertions(+), 32 deletions(-) diff --git a/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll b/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll index 17a8a57b953..45434ed2719 100644 --- a/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll +++ b/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s ; Store a <4 x i31> vector. @@ -75,38 +76,38 @@ define void @fun2(<8 x i32> %src, <8 x i31>* %p) ; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ; CHECK-NEXT: .cfi_offset %r14, -48 ; CHECK-NEXT: .cfi_offset %r15, -40 -; CHECK-DAG: vlgvf [[REG11:%r[0-9]+]], %v26, 1 -; CHECK-DAG: vlgvf [[REG12:%r[0-9]+]], %v26, 2 -; CHECK-DAG: risbgn [[REG13:%r[0-9]+]], [[REG11]], 0, 129, 62 -; CHECK-DAG: rosbg [[REG13]], [[REG12]], 2, 32, 31 -; CHECK-DAG: vlgvf %r0, %v26, 3 -; CHECK-DAG: rosbg [[REG13]], %r0, 33, 63, 0 -; CHECK-DAG: stc %r0, 30(%r2) -; CHECK-DAG: srlk %r1, %r0, 8 -; CHECK-DAG: vlgvf [[REG0:%r[0-9]+]], %v24, 1 -; CHECK-DAG: vlgvf [[REG1:%r[0-9]+]], %v24, 0 -; CHECK-DAG: sth %r1, 28(%r2) -; CHECK-DAG: vlgvf [[REG2:%r[0-9]+]], %v24, 2 -; CHECK-DAG: risbgn [[REG3:%r[0-9]+]], [[REG0]], 0, 133, 58 -; CHECK-DAG: rosbg [[REG3]], [[REG2]], 6, 36, 27 -; CHECK-DAG: sllg [[REG4:%r[0-9]+]], [[REG1]], 25 -; CHECK-DAG: rosbg [[REG4]], [[REG0]], 39, 63, 58 -; CHECK-DAG: vlgvf [[REG5:%r[0-9]+]], %v24, 3 -; CHECK-DAG: rosbg [[REG3]], [[REG5]], 37, 63, 60 -; CHECK-DAG: sllg [[REG6:%r[0-9]+]], [[REG4]], 8 -; CHECK-DAG: rosbg [[REG6]], [[REG3]], 56, 63, 8 -; CHECK-DAG: stg [[REG6]], 0(%r2) -; CHECK-DAG: srlg [[REG7:%r[0-9]+]], [[REG13]], 24 -; CHECK-DAG: st [[REG7]], 24(%r2) -; CHECK-DAG: vlgvf [[REG8:%r[0-9]+]], %v26, 0 -; CHECK-DAG: risbgn [[REG10:%r[0-9]+]], [[REG5]], 0, 131, 60 -; CHECK-DAG: rosbg [[REG10]], [[REG8]], 4, 34, 29 -; CHECK-DAG: sllg [[REG9:%r[0-9]+]], [[REG3]], 8 -; CHECK-DAG: rosbg [[REG10]], [[REG11]], 35, 63, 62 -; CHECK-DAG: rosbg [[REG9]], [[REG10]], 56, 63, 8 -; CHECK-DAG: stg [[REG9]], 8(%r2) -; CHECK-DAG: sllg %r0, [[REG10]], 8 -; CHECK-DAG: rosbg %r0, [[REG13]], 56, 63, 8 +; CHECK-NEXT: vlgvf %r0, %v26, 3 +; CHECK-NEXT: vlgvf %r4, %v24, 1 +; CHECK-NEXT: vlgvf %r3, %v24, 2 +; CHECK-NEXT: srlk %r1, %r0, 8 +; CHECK-NEXT: vlgvf %r5, %v24, 0 +; CHECK-NEXT: sth %r1, 28(%r2) +; CHECK-NEXT: risbgn %r1, %r4, 0, 133, 58 +; CHECK-NEXT: sllg %r5, %r5, 25 +; CHECK-NEXT: stc %r0, 30(%r2) +; CHECK-NEXT: rosbg %r1, %r3, 6, 36, 27 +; CHECK-NEXT: vlgvf %r3, %v24, 3 +; CHECK-NEXT: rosbg %r5, %r4, 39, 63, 58 +; CHECK-NEXT: sllg %r4, %r5, 8 +; CHECK-NEXT: rosbg %r1, %r3, 37, 63, 60 +; CHECK-NEXT: vlgvf %r5, %v26, 1 +; CHECK-NEXT: rosbg %r4, %r1, 56, 63, 8 +; CHECK-NEXT: stg %r4, 0(%r2) +; CHECK-NEXT: vlgvf %r4, %v26, 2 +; CHECK-NEXT: risbgn %r14, %r5, 0, 129, 62 +; CHECK-NEXT: risbgn %r3, %r3, 0, 131, 60 +; CHECK-NEXT: rosbg %r14, %r4, 2, 32, 31 +; CHECK-NEXT: rosbg %r14, %r0, 33, 63, 0 +; CHECK-NEXT: srlg %r0, %r14, 24 +; CHECK-NEXT: st %r0, 24(%r2) +; CHECK-NEXT: vlgvf %r0, %v26, 0 +; CHECK-NEXT: rosbg %r3, %r0, 4, 34, 29 +; CHECK-NEXT: sllg %r0, %r1, 8 +; CHECK-NEXT: rosbg %r3, %r5, 35, 63, 62 +; CHECK-NEXT: rosbg %r0, %r3, 56, 63, 8 +; CHECK-NEXT: stg %r0, 8(%r2) +; CHECK-NEXT: sllg %r0, %r3, 8 +; CHECK-NEXT: rosbg %r0, %r14, 56, 63, 8 ; CHECK-NEXT: stg %r0, 16(%r2) ; CHECK-NEXT: lmg %r14, %r15, 112(%r15) ; CHECK-NEXT: br %r14 -- 2.40.0