From 023ae40959dfe9fce5ddda9b57563f167a8fbed2 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 17 Apr 2017 01:51:16 +0000 Subject: [PATCH] [InstCombine] Add test cases for missing support for turning vector sdiv into udiv. NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300434 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/Transforms/InstCombine/div-shift.ll | 15 +++++++++++++++ test/Transforms/InstCombine/div.ll | 11 +++++++++++ 2 files changed, 26 insertions(+) diff --git a/test/Transforms/InstCombine/div-shift.ll b/test/Transforms/InstCombine/div-shift.ll index 517313ed8e4..5642241c96f 100644 --- a/test/Transforms/InstCombine/div-shift.ll +++ b/test/Transforms/InstCombine/div-shift.ll @@ -16,6 +16,21 @@ entry: ret i32 %d } +define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) { +; CHECK-LABEL: @t1vec( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CONV:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i32> +; CHECK-NEXT: [[S:%.*]] = shl nuw <2 x i32> , [[Y:%.*]] +; CHECK-NEXT: [[D:%.*]] = sdiv <2 x i32> [[CONV]], [[S]] +; CHECK-NEXT: ret <2 x i32> [[D]] +; +entry: + %conv = zext <2 x i16> %x to <2 x i32> + %s = shl <2 x i32> , %y + %d = sdiv <2 x i32> %conv, %s + ret <2 x i32> %d +} + ; rdar://11721329 define i64 @t2(i64 %x, i32 %y) { ; CHECK-LABEL: @t2( diff --git a/test/Transforms/InstCombine/div.ll b/test/Transforms/InstCombine/div.ll index a037607267a..99cd6962e95 100644 --- a/test/Transforms/InstCombine/div.ll +++ b/test/Transforms/InstCombine/div.ll @@ -388,6 +388,17 @@ define i32 @test35(i32 %A) { ret i32 %mul } +define <2 x i32> @test35vec(<2 x i32> %A) { +; CHECK-LABEL: @test35vec( +; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A:%.*]], +; CHECK-NEXT: [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], +; CHECK-NEXT: ret <2 x i32> [[MUL]] +; + %and = and <2 x i32> %A, + %mul = sdiv exact <2 x i32> %and, + ret <2 x i32> %mul +} + define i32 @test36(i32 %A) { ; CHECK-LABEL: @test36( ; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647 -- 2.40.0