]> granicus.if.org Git - llvm/log
llvm
5 years ago[InstCombine] Signed saturation patterns master origin/HEAD origin/master
David Green [Tue, 22 Oct 2019 15:39:47 +0000 (15:39 +0000)]
[InstCombine] Signed saturation patterns

This adds an instcombine matcher for code that attempts to perform signed
saturating arithmetic by casting to a higher type. Unsigned cases are already
matched, this adds extra matches for the more complex signed cases, which
involves matching the min(max(add a b)) nodes with proper extends to ensure
legality.

Differential Revision: https://reviews.llvm.org/D68651

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375505 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] Signed saturation tests. NFC
David Green [Tue, 22 Oct 2019 14:49:40 +0000 (14:49 +0000)]
[InstCombine] Signed saturation tests. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375503 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MIParser] Set RegClassOrRegBank during instruction parsing
Petar Avramovic [Tue, 22 Oct 2019 14:25:37 +0000 (14:25 +0000)]
[MIParser] Set RegClassOrRegBank during instruction parsing

MachineRegisterInfo::createGenericVirtualRegister sets
RegClassOrRegBank to static_cast<RegisterBank *>(nullptr).
MIParser on the other hand doesn't. When we attempt to constrain
Register Class on such VReg, additional COPY is generated.
This way we avoid COPY instructions showing in test that have MIR
input while they are not present with llvm-ir input that was used
to create given MIR for a -run-pass test.

Differential Revision: https://reviews.llvm.org/D68946

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375502 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MIPS GlobalISel] Select MSA vector generic and builtin add
Petar Avramovic [Tue, 22 Oct 2019 13:51:57 +0000 (13:51 +0000)]
[MIPS GlobalISel] Select MSA vector generic and builtin add

Select vector G_ADD for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
__builtin_msa_addv_<format> will be transformed into G_ADD
in legalizeIntrinsic and selected in the same way.
__builtin_msa_addvi_<format> will be directly selected into
ADDVI_<format> in legalizeIntrinsic. MIR tests for it have
unnecessary additional copies. Capture current state of tests
with run-pass=legalizer with a test in test/CodeGen/MIR/Mips.

Differential Revision: https://reviews.llvm.org/D68984

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375501 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ThinLTO] Add code comment. NFC
Eugene Leviant [Tue, 22 Oct 2019 12:57:23 +0000 (12:57 +0000)]
[ThinLTO] Add code comment. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375500 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Alignment][NFC] Convert StoreInst to MaybeAlign
Guillaume Chatelet [Tue, 22 Oct 2019 12:55:32 +0000 (12:55 +0000)]
[Alignment][NFC] Convert StoreInst to MaybeAlign

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69303

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375499 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Alignment][NFC] Convert LoadInst to MaybeAlign
Guillaume Chatelet [Tue, 22 Oct 2019 12:35:55 +0000 (12:35 +0000)]
[Alignment][NFC] Convert LoadInst to MaybeAlign

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69302

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375498 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[PowerPC] Turn on CR-Logical reducer pass
Nemanja Ivanovic [Tue, 22 Oct 2019 12:20:38 +0000 (12:20 +0000)]
[PowerPC] Turn on CR-Logical reducer pass

This re-commits r375152 which was pulled in r375233 because it broke
the EXPENSIVE_CHECKS bot on Windows.

The reason for the failure was a bug in the pass that the commit turned
on by default. This patch fixes that bug and turns the pass back on.
This patch has been verified on the buildbot that originally failed
thanks to Simon Pilgrim.

Differential revision: https://reviews.llvm.org/D52431

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375497 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Alignment][NFC] Use MaybeAlign in AttrBuilder
Guillaume Chatelet [Tue, 22 Oct 2019 11:57:52 +0000 (11:57 +0000)]
[Alignment][NFC] Use MaybeAlign in AttrBuilder

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69300

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375496 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Alignment][NFC] Attributes use Align/MaybeAlign
Guillaume Chatelet [Tue, 22 Oct 2019 09:51:06 +0000 (09:51 +0000)]
[Alignment][NFC] Attributes use Align/MaybeAlign

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: jholewinski, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69278

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375495 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ThinLTO] Don't internalize during promotion
Eugene Leviant [Tue, 22 Oct 2019 09:24:12 +0000 (09:24 +0000)]
[ThinLTO] Don't internalize during promotion

Differential revision: https://reviews.llvm.org/D69107

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375493 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[LLVMDebugInfoPDB] - Use cantFail() instead of assert().
George Rimar [Tue, 22 Oct 2019 08:52:45 +0000 (08:52 +0000)]
[LLVMDebugInfoPDB] - Use cantFail() instead of assert().

Currently injected-sources-native.test fails with "Expected<T>
value was in success state.
(Note: Expected<T> values in success mode must still be checked
prior to being destroyed)"
when llvm is compiled with LLVM_ENABLE_ABI_BREAKING_CHECKS in Release.

The problem is that getStringForID returns Expected<StringRef>
and Expected value must always be checked, even if it is in success state.
Checking with assert only helps in Debug and is wrong.

Differential revision: https://reviews.llvm.org/D69251

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375492 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[CMake] [WinMsvc] Look for includes and libs in ${MSVC_BASE}/atlmfc
Martin Storsjo [Tue, 22 Oct 2019 06:36:27 +0000 (06:36 +0000)]
[CMake] [WinMsvc] Look for includes and libs in ${MSVC_BASE}/atlmfc

This is necessary if building with the DIA SDK enabled.

Differential Revision: https://reviews.llvm.org/D69240

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375486 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[CMake] Allow overriding MSVC_DIA_SDK_DIR via CMake
Martin Storsjo [Tue, 22 Oct 2019 06:36:21 +0000 (06:36 +0000)]
[CMake] Allow overriding MSVC_DIA_SDK_DIR via CMake

This eases using it in cross-msvc setups.

Differential Revision: https://reviews.llvm.org/D69239

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375485 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agogn build: Merge r375483
GN Sync Bot [Tue, 22 Oct 2019 05:09:35 +0000 (05:09 +0000)]
gn build: Merge r375483

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375484 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[lit] Move increase_process_limit to ParallelRun
Julian Lettner [Tue, 22 Oct 2019 01:13:30 +0000 (01:13 +0000)]
[lit] Move increase_process_limit to ParallelRun

Increasing the process limit only makes sense when we use multiple
processes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375474 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86][BMI] Pull out schedule classes from bmi_andn<> and bmi_bls<>
Simon Pilgrim [Mon, 21 Oct 2019 23:41:40 +0000 (23:41 +0000)]
[X86][BMI] Pull out schedule classes from bmi_andn<> and bmi_bls<>

Stop hardwiring classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375470 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86][SSE] Add OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1))) -> MOVMSK+CMP reduction combine
Simon Pilgrim [Mon, 21 Oct 2019 22:36:31 +0000 (22:36 +0000)]
[X86][SSE] Add OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1))) -> MOVMSK+CMP reduction combine

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375463 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86][SSE] Add OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1))) movmsk v2X64 tests
Simon Pilgrim [Mon, 21 Oct 2019 22:36:07 +0000 (22:36 +0000)]
[X86][SSE] Add OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1))) movmsk v2X64 tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375462 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[examples] Add a dependency on ExecutionEngine to LLJITWithObjectCache example.
Lang Hames [Mon, 21 Oct 2019 22:29:29 +0000 (22:29 +0000)]
[examples] Add a dependency on ExecutionEngine to LLJITWithObjectCache example.

ExecutionEngine.cpp contains the anchor() for the ObjectCache base class, so we
need an explicit dependency on it.

Patch by Stephen Neuendorffer. Thanks Stephen!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375461 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU/GlobalISel: Legalize fast unsafe FDIV
Austin Kerbow [Mon, 21 Oct 2019 22:18:26 +0000 (22:18 +0000)]
AMDGPU/GlobalISel: Legalize fast unsafe FDIV

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69231

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375460 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[lit] Simplify test scheduling via multiprocessing.Pool
Julian Lettner [Mon, 21 Oct 2019 21:57:18 +0000 (21:57 +0000)]
[lit] Simplify test scheduling via multiprocessing.Pool

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375458 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Select basic interp directly from intrinsics
Matt Arsenault [Mon, 21 Oct 2019 21:49:44 +0000 (21:49 +0000)]
AMDGPU: Select basic interp directly from intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375457 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[lit] Remove redundancy from names and comments
Julian Lettner [Mon, 21 Oct 2019 21:41:59 +0000 (21:41 +0000)]
[lit] Remove redundancy from names and comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375456 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[CVP] No-wrap deduction for `shl`
Roman Lebedev [Mon, 21 Oct 2019 21:31:19 +0000 (21:31 +0000)]
[CVP] No-wrap deduction for `shl`

Summary:
This is the last `OverflowingBinaryOperator` for which we don't deduce flags.
D69217 taught `ConstantRange::makeGuaranteedNoWrapRegion()` about it.

The effect is better than of the `mul` patch (D69203):

| statistic                              |     old |     new | delta | % change |
| correlated-value-propagation.NumAddNUW |    7145 |    7144 |    -1 | -0.0140% |
| correlated-value-propagation.NumAddNW  |   12126 |   12125 |    -1 | -0.0082% |
| correlated-value-propagation.NumAnd    |     443 |     446 |     3 |  0.6772% |
| correlated-value-propagation.NumNSW    |    5986 |    7158 |  1172 | 19.5790% |
| correlated-value-propagation.NumNUW    |   10512 |   13304 |  2792 | 26.5601% |
| correlated-value-propagation.NumNW     |   16498 |   20462 |  3964 | 24.0272% |
| correlated-value-propagation.NumShlNSW |       0 |    1172 |  1172 |          |
| correlated-value-propagation.NumShlNUW |       0 |    2793 |  2793 |          |
| correlated-value-propagation.NumShlNW  |       0 |    3965 |  3965 |          |
| instcount.NumAShrInst                  |   13824 |   13790 |   -34 | -0.2459% |
| instcount.NumAddInst                   |  277584 |  277586 |     2 |  0.0007% |
| instcount.NumAndInst                   |   66061 |   66056 |    -5 | -0.0076% |
| instcount.NumBrInst                    |  709153 |  709147 |    -6 | -0.0008% |
| instcount.NumICmpInst                  |  483709 |  483708 |    -1 | -0.0002% |
| instcount.NumSExtInst                  |   79497 |   79496 |    -1 | -0.0013% |
| instcount.NumShlInst                   |   40691 |   40654 |   -37 | -0.0909% |
| instcount.NumSubInst                   |   61997 |   61996 |    -1 | -0.0016% |
| instcount.NumZExtInst                  |   68208 |   68211 |     3 |  0.0044% |
| instcount.TotalBlocks                  |  843916 |  843910 |    -6 | -0.0007% |
| instcount.TotalInsts                   | 7387528 | 7387448 |   -80 | -0.0011% |

Reviewers: nikic, reames, sanjoy, timshen

Reviewed By: nikic

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69277

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375455 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[GISel][CombinerHelper] Add a combine turning shuffle_vector into concat_vectors
Quentin Colombet [Mon, 21 Oct 2019 20:39:58 +0000 (20:39 +0000)]
[GISel][CombinerHelper] Add a combine turning shuffle_vector into concat_vectors

Teach the CombinerHelper how to turn shuffle_vectors, that
concatenate vectors, into concat_vectors and add this combine
to the AArch64 pre-legalizer combiner.

Differential Revision: https://reviews.llvm.org/D69149

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375452 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Use CopyToReg for interp intrinsic lowering
Matt Arsenault [Mon, 21 Oct 2019 19:53:49 +0000 (19:53 +0000)]
AMDGPU: Use CopyToReg for interp intrinsic lowering

This doesn't use the default value, so doesn't benefit from the hack
to help optimize it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375450 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Erase redundant redefs of m0 in SIFoldOperands
Matt Arsenault [Mon, 21 Oct 2019 19:53:46 +0000 (19:53 +0000)]
AMDGPU: Erase redundant redefs of m0 in SIFoldOperands

Only handle simple inter-block redefs of m0 to the same value. This
avoids interference from redefs of m0 in SILoadStoreOptimzer. I was
initially teaching that pass to ignore redefs of m0, but having them
not exist beforehand is much simpler.

This is in preparation for deleting the current special m0 handling in
SIFixSGPRCopies to allow the register coalescer to handle the
difficult cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375449 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Stop adding m0 implicit def to SGPR spills
Matt Arsenault [Mon, 21 Oct 2019 19:42:29 +0000 (19:42 +0000)]
AMDGPU: Stop adding m0 implicit def to SGPR spills

r375293 removed the SGPR spilling with scalar stores path, so this is
no longer necessary. This also always had the defect of adding the def
even when this path wasn't in use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375448 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Slightly restructure m0 init code
Matt Arsenault [Mon, 21 Oct 2019 19:42:26 +0000 (19:42 +0000)]
AMDGPU: Slightly restructure m0 init code

This will allow using another operation to produce the glue in a
future change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375447 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AMDGPU] Select AGPR in PHI operand legalization
Stanislav Mekhanoshin [Mon, 21 Oct 2019 19:25:27 +0000 (19:25 +0000)]
[AMDGPU] Select AGPR in PHI operand legalization

If a PHI defines AGPR legalize its operands to AGPR.
At the moment we can get an AGPR PHI with VGPR operands.
I am not aware of any problems as it seems to be handled
gracefully in RA, but this is not right anyway.

It also slightly decreases VGPR pressure in some cases
because we do not have to a copy via VGPR.

Differential Revision: https://reviews.llvm.org/D69206

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375446 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] Rename matchBitOpReduction to matchScalarReduction. NFCI.
Simon Pilgrim [Mon, 21 Oct 2019 19:19:50 +0000 (19:19 +0000)]
[X86] Rename matchBitOpReduction to matchScalarReduction. NFCI.

This doesn't need to be just for bitops, but the ops do need to be fully associative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375445 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoReverted r375425 as it broke some buildbots.
Sander de Smalen [Mon, 21 Oct 2019 19:11:40 +0000 (19:11 +0000)]
Reverted r375425 as it broke some buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375444 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC][CVP] Add `shl` no-wrap deduction test coverage
Roman Lebedev [Mon, 21 Oct 2019 18:35:26 +0000 (18:35 +0000)]
[NFC][CVP] Add `shl` no-wrap deduction test coverage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375441 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoPrune Pass.h include from DataLayout.h. NFCI
Bjorn Pettersson [Mon, 21 Oct 2019 17:51:54 +0000 (17:51 +0000)]
Prune Pass.h include from DataLayout.h. NFCI

Summary:
Reduce include dependencies by no longer including Pass.h from
DataLayout.h. That include seemed irrelevant to DataLayout, as
well as being irrelevant to several users of DataLayout.

Reviewers: rnk

Reviewed By: rnk

Subscribers: mehdi_amini, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D69261

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375436 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[PowerPC] Regenerate test for D52431
Simon Pilgrim [Mon, 21 Oct 2019 17:45:51 +0000 (17:45 +0000)]
[PowerPC] Regenerate test for D52431

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375435 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC] Add missing include to fix modules build
Raphael Isemann [Mon, 21 Oct 2019 17:43:38 +0000 (17:43 +0000)]
[NFC] Add missing include to fix modules build

This header doesn't seem to be parsable on its own and breaks the module build therefore with
the following error:

While building module 'LLVM_Backend' imported from llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp:14:
In file included from <module-includes>:62:
llvm-project/llvm/include/llvm/CodeGen/MachinePipeliner.h:91:20: error: declaration of 'AAResultsWrapperPass' must be imported from module 'LLVM_Analysis.AliasAnalysis' before it is required
    AU.addRequired<AAResultsWrapperPass>();
                   ^
llvm-project/llvm/include/llvm/Analysis/AliasAnalysis.h:1157:7: note: previous declaration is here
class AAResultsWrapperPass : public FunctionPass {
      ^
llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp:14:10: fatal error: could not build module 'LLVM_Backend'
 ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2 errors generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375433 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoSystemZISelLowering - supportedAddressingMode - silence static analyzer dyn_cast...
Simon Pilgrim [Mon, 21 Oct 2019 17:16:03 +0000 (17:16 +0000)]
SystemZISelLowering - supportedAddressingMode - silence static analyzer dyn_cast<> null dereference warning. NFCI.

The static analyzer is warning about a potential null dereference, but we should be able to use cast<> directly and if not assert will fire for us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375430 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoGVNHoist - silence static analyzer dyn_cast<> null dereference warning in hasEHOrLoad...
Simon Pilgrim [Mon, 21 Oct 2019 17:15:49 +0000 (17:15 +0000)]
GVNHoist - silence static analyzer dyn_cast<> null dereference warning in hasEHOrLoadsOnPath call. NFCI.

The static analyzer is warning about a potential null dereference, but we should be able to use cast<> directly and if not assert will fire for us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375429 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoGuardWidening - silence static analyzer null dereference warning with assertion....
Simon Pilgrim [Mon, 21 Oct 2019 17:15:37 +0000 (17:15 +0000)]
GuardWidening - silence static analyzer null dereference warning with assertion. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375428 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoCrossDSOCFI - silence static analyzer dyn_cast<> null dereference warning. NFCI.
Simon Pilgrim [Mon, 21 Oct 2019 17:15:25 +0000 (17:15 +0000)]
CrossDSOCFI - silence static analyzer dyn_cast<> null dereference warning. NFCI.

The static analyzer is warning about a potential null dereference, but we should be able to use cast<> directly and if not assert will fire for us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375427 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoIndVarSimplify - silence static analyzer dyn_cast<> null dereference warning. NFCI.
Simon Pilgrim [Mon, 21 Oct 2019 17:15:05 +0000 (17:15 +0000)]
IndVarSimplify - silence static analyzer dyn_cast<> null dereference warning. NFCI.

The static analyzer is warning about a potential null dereference, but we should be able to use cast<> directly and if not assert will fire for us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375426 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AArch64][DebugInfo] Do not recompute CalleeSavedStackSize (Take 2)
Sander de Smalen [Mon, 21 Oct 2019 17:12:56 +0000 (17:12 +0000)]
[AArch64][DebugInfo] Do not recompute CalleeSavedStackSize (Take 2)

Commit message from D66935:

This patch fixes a bug exposed by D65653 where a subsequent invocation
of `determineCalleeSaves` ends up with a different size for the callee
save area, leading to different frame-offsets in debug information.

In the invocation by PEI, `determineCalleeSaves` tries to determine
whether it needs to spill an extra callee-saved register to get an
emergency spill slot. To do this, it calls 'estimateStackSize' and
manually adds the size of the callee-saves to this. PEI then allocates
the spill objects for the callee saves and the remaining frame layout
is calculated accordingly.

A second invocation in LiveDebugValues causes estimateStackSize to return
the size of the stack frame including the callee-saves. Given that the
size of the callee-saves is added to this, these callee-saves are counted
twice, which leads `determineCalleeSaves` to believe the stack has
become big enough to require spilling an extra callee-save as emergency
spillslot. It then updates CalleeSavedStackSize with a larger value.

Since CalleeSavedStackSize is used in the calculation of the frame
offset in getFrameIndexReference, this leads to incorrect offsets for
variables/locals when this information is recalculated after PEI.

This patch fixes the lldb unit tests in `functionalities/thread/concurrent_events/*`

Changes after D66935:

Ensures AArch64FunctionInfo::getCalleeSavedStackSize does not return
the uninitialized CalleeSavedStackSize when running `llc` on a specific
pass where the MIR code has already been expected to have gone through PEI.

Instead, getCalleeSavedStackSize (when passed the MachineFrameInfo) will try
to recalculate the CalleeSavedStackSize from the CalleeSavedInfo. In debug
mode, the compiler will assert the recalculated size equals the cached
size as calculated through a call to determineCalleeSaves.

This fixes two tests:
  test/DebugInfo/AArch64/asan-stack-vars.mir
  test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir
that otherwise fail when compiled using msan.

Reviewed By: omjavaid, efriedma

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375425 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC] Cleanup with variable name IsPPC64 & IsDarwin
Xiangling Liao [Mon, 21 Oct 2019 15:36:13 +0000 (15:36 +0000)]
[NFC] Cleanup with variable name IsPPC64 & IsDarwin

Clean up PPCAsmPrinter with IsPPC64 and IsDarwin.

Differential Revision: https://reviews.llvm.org/D69259

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375420 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Alignment][NFC] Finish transition for `Loads`
Guillaume Chatelet [Mon, 21 Oct 2019 15:10:26 +0000 (15:10 +0000)]
[Alignment][NFC] Finish transition for `Loads`

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, asbirlea, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69253

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375419 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoPre-commit test cases for D64713.
Jay Foad [Mon, 21 Oct 2019 15:01:59 +0000 (15:01 +0000)]
Pre-commit test cases for D64713.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375418 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Types] Define a getWithNewBitWidth for Types and make use of it
David Green [Mon, 21 Oct 2019 14:51:49 +0000 (14:51 +0000)]
[Types] Define a getWithNewBitWidth for Types and make use of it

This is designed to change the bitwidth of a type without altering the number
of vector lanes. Also useful in D68651. Otherwise an NFC.

Differential Revision: https://reviews.llvm.org/D69139

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375417 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Alignment][NFC] Instructions::getLoadStoreAlignment
Guillaume Chatelet [Mon, 21 Oct 2019 14:49:28 +0000 (14:49 +0000)]
[Alignment][NFC] Instructions::getLoadStoreAlignment

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375416 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM] Extra qdadd patterns
David Green [Mon, 21 Oct 2019 14:06:49 +0000 (14:06 +0000)]
[ARM] Extra qdadd patterns

This adds some new qdadd patterns to go along with the other recently added
qadd's.

Differential Revision: https://reviews.llvm.org/D68999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375414 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Alignment][NFC] Add a helper function to DataLayout
Guillaume Chatelet [Mon, 21 Oct 2019 13:58:33 +0000 (13:58 +0000)]
[Alignment][NFC] Add a helper function to DataLayout

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69258

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375413 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[docs][llvm-ar] Update llvm-ar command guide
Owen Reynolds [Mon, 21 Oct 2019 13:13:31 +0000 (13:13 +0000)]
[docs][llvm-ar] Update llvm-ar command guide

The llvm-ar command guide had not been updated in some time, it was
missing current functionality and contained information that was out
of date. This change:
- Updates the use of reStructuredText directives, as seen in other tools
  command guides.
- Updates the command synopsis.
- Updates the descriptions of the tool behaviour.
- Updates the options section.
- Adds details of MRI script functionality.
- Removes the sections "Standards" and "File Format"

Differential Revision: https://reviews.llvm.org/D68998

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375412 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM] Add qadd lowering from a sadd_sat
David Green [Mon, 21 Oct 2019 12:33:46 +0000 (12:33 +0000)]
[ARM] Add qadd lowering from a sadd_sat

This lowers a sadd_sat to a qadd by treating it as legal. Also adds qsub at the
same time.

The qadd instruction sets the q flag, but we already have many cases where we
do not model this in llvm.

Differential Revision: https://reviews.llvm.org/D68976

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375411 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Alignment][NFC] TargetCallingConv::setByValAlign
Guillaume Chatelet [Mon, 21 Oct 2019 12:05:33 +0000 (12:05 +0000)]
[Alignment][NFC] TargetCallingConv::setByValAlign

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69248

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375410 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoSimplify usage of setFPAttrs.
Jay Foad [Mon, 21 Oct 2019 11:32:41 +0000 (11:32 +0000)]
Simplify usage of setFPAttrs.

In some cases using the return value of setFPAttrs simplifies the code.
In other cases it complicates the code with ugly casts, so stop doing
it. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375409 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[llvm/Object] - Make ELFObjectFile::getRelocatedSection return Expected<section_iterator>
George Rimar [Mon, 21 Oct 2019 11:06:38 +0000 (11:06 +0000)]
[llvm/Object] - Make ELFObjectFile::getRelocatedSection return Expected<section_iterator>

It returns just a section_iterator currently and have a report_fatal_error call inside.
This change adds a way to return errors and handle them on caller sides.

The patch also changes/improves current users and adds test cases.

Differential revision: https://reviews.llvm.org/D69167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375408 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Alignment][NFC] TargetCallingConv::setOrigAlign and TargetLowering::getABIAlignmentF...
Guillaume Chatelet [Mon, 21 Oct 2019 11:01:55 +0000 (11:01 +0000)]
[Alignment][NFC] TargetCallingConv::setOrigAlign and TargetLowering::getABIAlignmentForCallingConv

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: sdardis, hiraditya, jrtc27, atanasyan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69243

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375407 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix llvm signal tests build.
David Carlier [Mon, 21 Oct 2019 10:44:20 +0000 (10:44 +0000)]
Fix llvm signal tests build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375406 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[obj2yaml] - Fix a comment. NFC.
George Rimar [Mon, 21 Oct 2019 10:40:43 +0000 (10:40 +0000)]
[obj2yaml] - Fix a comment. NFC.

I forgot to address this nit before committing..

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375405 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[obj2yaml] - Stop triggering UB when dumping corrupted strings.
George Rimar [Mon, 21 Oct 2019 10:38:03 +0000 (10:38 +0000)]
[obj2yaml] - Stop triggering UB when dumping corrupted strings.

We have a following code to find quote type:

if (isspace(S.front()) || isspace(S.back()))
...

Problem is that:

"int isspace( int ch ): The behavior is undefined if the value of
ch is not representable as unsigned char and is not equal to EOF."
(https://en.cppreference.com/w/cpp/string/byte/isspace)

This patch shows how this UB can be triggered and fixes an issue.

Differential revision: https://reviews.llvm.org/D69160

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375404 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MemCpyOpt] Fixing Incorrect Code Motion while Handling Aggregate Type Values
Sam Elliott [Mon, 21 Oct 2019 10:00:34 +0000 (10:00 +0000)]
[MemCpyOpt] Fixing Incorrect Code Motion while Handling Aggregate Type Values

Summary:
When MemCpyOpt is handling aggregate type values, if an instruction (let's call it P) between the targeting load (L) and store (S) clobbers the source pointer of L, it will try to hoist S before P. This process will also hoist S's data dependency instructions.

However, the current implementation has a bug that if one of S's dependency instructions is //also// a user of P, MemCpyOpt will not prevent it from being hoisted above P and cause a use-before-define error. For example, in the newly added test file (i.e. `aggregate-type-crash.ll`), it will try to hoist both `store %my_struct %1, %my_struct* %3` and its dependent, `%3 = bitcast i8* %2 to %my_struct*`, above `%2 = call i8* @my_malloc(%my_struct* %0)`. Creating the following BB:
```
entry:
  %1 = bitcast i8* %4 to %my_struct*
  %2 = bitcast %my_struct* %1 to i8*
  %3 = bitcast %my_struct* %0 to i8*
  call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %2, i8* align 4 %3, i64 8, i1 false)
  %4 = call i8* @my_malloc(%my_struct* %0)
  ret void
```
Where there is a use-before-define error between `%1` and `%4`.

Update: The compiler for the Pony Programming Language [also encounter the same bug](https://github.com/ponylang/ponyc/issues/3140)

Patch by Min-Yih Hsu (myhsu)

Reviewers: eugenis, pcc, dblaikie, dneilson, t.p.northover, lattner

Reviewed By: eugenis

Subscribers: lenary, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375403 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM] Lower sadd_sat to qadd8 and qadd16
David Green [Mon, 21 Oct 2019 09:53:38 +0000 (09:53 +0000)]
[ARM] Lower sadd_sat to qadd8 and qadd16

Lower the target independent signed saturating intrinsics to qadd8 and qadd16.
This custom lowers them from a sadd_sat, catching the node early before it is
promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a
qadd8/qadd16, so that we can call demand bits on it to show that it does not
use the upper bits.

Also handles QSUB8 and QSUB16.

Differential Revision: https://reviews.llvm.org/D68974

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375402 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM] Add and adjust saturation tests for upcoming qadd changes. NFC
David Green [Mon, 21 Oct 2019 09:43:37 +0000 (09:43 +0000)]
[ARM] Add and adjust saturation tests for upcoming qadd changes. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375401 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoUse Align for TFL::TransientStackAlignment
Guillaume Chatelet [Mon, 21 Oct 2019 08:31:25 +0000 (08:31 +0000)]
Use Align for TFL::TransientStackAlignment

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: arsenm, dschuff, jyknight, sdardis, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, fedor.sergeev, jrtc27, atanasyan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69216

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375398 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC][InstCombine] Fixup comments
Roman Lebedev [Mon, 21 Oct 2019 08:21:54 +0000 (08:21 +0000)]
[NFC][InstCombine] Fixup comments

As noted in post-commit review of rL375378375378.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375397 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[CVP] Deduce no-wrap on `mul`
Roman Lebedev [Mon, 21 Oct 2019 08:21:44 +0000 (08:21 +0000)]
[CVP] Deduce no-wrap on `mul`

Summary:
`ConstantRange::makeGuaranteedNoWrapRegion()` knows how to deal with `mul`
since rL335646, there is exhaustive test coverage.
This is already used by CVP's `processOverflowIntrinsic()`,
and by SCEV's `StrengthenNoWrapFlags()`

That being said, currently, this doesn't help much in the end:
| statistic                              |     old |     new | delta | percentage |
| correlated-value-propagation.NumMulNSW |       4 |     275 |   271 |   6775.00% |
| correlated-value-propagation.NumMulNUW |       4 |    1323 |  1319 |  32975.00% |
| correlated-value-propagation.NumMulNW  |       8 |    1598 |  1590 |  19875.00% |
| correlated-value-propagation.NumNSW    |    5715 |    5986 |   271 |      4.74% |
| correlated-value-propagation.NumNUW    |    9193 |   10512 |  1319 |     14.35% |
| correlated-value-propagation.NumNW     |   14908 |   16498 |  1590 |     10.67% |
| instcount.NumAddInst                   |  275871 |  275869 |    -2 |      0.00% |
| instcount.NumBrInst                    |  708234 |  708232 |    -2 |      0.00% |
| instcount.NumMulInst                   |   43812 |   43810 |    -2 |      0.00% |
| instcount.NumPHIInst                   |  316786 |  316784 |    -2 |      0.00% |
| instcount.NumTruncInst                 |   62165 |   62167 |     2 |      0.00% |
| instcount.NumUDivInst                  |    2528 |    2526 |    -2 |     -0.08% |
| instcount.TotalBlocks                  |  842995 |  842993 |    -2 |      0.00% |
| instcount.TotalInsts                   | 7376486 | 7376478 |    -8 |      0.00% |
(^ test-suite plain, tests still pass)

Reviewers: nikic, reames, luqmana, sanjoy, timshen

Reviewed By: reames

Subscribers: hiraditya, javed.absar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69203

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375396 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] Allow values with multiple users in SimplifyDemandedVectorElts
Piotr Sobczak [Mon, 21 Oct 2019 08:12:47 +0000 (08:12 +0000)]
[InstCombine] Allow values with multiple users in SimplifyDemandedVectorElts

Summary:
Allow for ignoring the check for a single use in SimplifyDemandedVectorElts
to be able to simplify operands if DemandedElts is known to contain
the union of elements used by all users.
It is a responsibility of a caller of SimplifyDemandedVectorElts to
supply correct DemandedElts.

Simplify a series of extractelement instructions if only a subset of
elements is used.

Reviewers: reames, arsenm, majnemer, nhaehnle

Reviewed By: nhaehnle

Subscribers: wdng, jvesely, nhaehnle, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375395 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agogn build: Merge r375390
GN Sync Bot [Mon, 21 Oct 2019 08:06:38 +0000 (08:06 +0000)]
gn build: Merge r375390

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375393 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[LLDB] [Windows] Initial support for ARM register contexts
Martin Storsjo [Mon, 21 Oct 2019 08:02:34 +0000 (08:02 +0000)]
[LLDB] [Windows] Initial support for ARM register contexts

Differential Revision: https://reviews.llvm.org/D69226

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375392 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[IR] Fix mayReadFromMemory() for writeonly calls
Yevgeny Rouban [Mon, 21 Oct 2019 06:52:08 +0000 (06:52 +0000)]
[IR] Fix mayReadFromMemory() for writeonly calls

Current implementation of Instruction::mayReadFromMemory()
returns !doesNotAccessMemory() which is !ReadNone. This
does not take into account that the writeonly attribute
also indicates that the call does not read from memory.

The patch changes the predicate to !doesNotReadMemory()
that reflects the intended behavior.

Differential Revision: https://reviews.llvm.org/D69086

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375389 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[BPF] fix indirect call assembly code
Yonghong Song [Mon, 21 Oct 2019 03:22:03 +0000 (03:22 +0000)]
[BPF] fix indirect call assembly code

Currently, for indirect call, the assembly code printed out as
  callx <imm>
This is not right, it should be
  callx <reg>

Fixed the issue with proper format.

Differential Revision: https://reviews.llvm.org/D69229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375386 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Attributor][FIX] Silence sign-compare warning
Johannes Doerfert [Mon, 21 Oct 2019 01:29:10 +0000 (01:29 +0000)]
[Attributor][FIX] Silence sign-compare warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375384 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Attributor] Teach AANoCapture to use information in-flight more aggressively
Johannes Doerfert [Mon, 21 Oct 2019 00:48:42 +0000 (00:48 +0000)]
[Attributor] Teach AANoCapture to use information in-flight more aggressively

AAReturnedValues, AAMemoryBehavior, and AANoUnwind, can provide
information that helps during the tracking or even justifies no-capture.
We now use this information and enable no-capture in some test cases
designed a long while a ago for these cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375382 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] Check Subtarget.hasSSE3() before calling shouldUseHorizontalOp and emitting...
Craig Topper [Sun, 20 Oct 2019 23:54:19 +0000 (23:54 +0000)]
[X86] Check Subtarget.hasSSE3() before calling shouldUseHorizontalOp and emitting X86ISD::FHADD in LowerUINT_TO_FP_i64.

This was a regression from r375341.

Fixes PR43729.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375381 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[IndVars] Add a todo to reflect a further oppurtunity identified in D69009
Philip Reames [Sun, 20 Oct 2019 23:44:01 +0000 (23:44 +0000)]
[IndVars] Add a todo to reflect a further oppurtunity identified in D69009

Nikita pointed out an oppurtunity, might as well document it in the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375380 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[IndVars] Eliminate loop exits with equivalent exit counts
Philip Reames [Sun, 20 Oct 2019 23:38:02 +0000 (23:38 +0000)]
[IndVars] Eliminate loop exits with equivalent exit counts

We can end up with two loop exits whose exit counts are equivalent, but whose textual representation is different and non-obvious. For the sub-case where we have a series of exits which dominate one another (common), eliminate any exits which would iterate *after* a previous exit on the exiting iteration.

As noted in the TODO being removed, I'd always thought this was a good idea, but I've now seen this in a real workload as well.

Interestingly, in review, Nikita pointed out there's let another oppurtunity to leverage SCEV's reasoning.  If we kept track of the min of dominanting exits so far, we could discharge exits with EC >= MDE.  This is less powerful than the existing transform (since later exits aren't considered), but potentially more powerful for any case where SCEV can prove a >= b, but neither a == b or a > b.  I don't have an example to illustrate that oppurtunity, but won't be suprised if we find one and return to handle that case as well.

Differential Revision: https://reviews.llvm.org/D69009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375379 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.
Roman Lebedev [Sun, 20 Oct 2019 20:52:06 +0000 (20:52 +0000)]
[InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.

In this pattern, all the "magic" bits that we'd `add` are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups

It is possible that `haveNoCommonBitsSet()` should be taught about this
pattern so that we never have an `add` variant, but the reasoning would
need to be recursive (because of that `select`), so i'm not really sure
that would be worth it just yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375378 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC][InstCombine] conditional sign-extend of high-bit-extract: 'and' pat. can be...
Roman Lebedev [Sun, 20 Oct 2019 20:51:37 +0000 (20:51 +0000)]
[NFC][InstCombine] conditional sign-extend of high-bit-extract: 'and' pat. can be 'or' pattern.

In this pattern, all the "magic" bits that we'd add are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375377 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agogn build: Merge r375375
GN Sync Bot [Sun, 20 Oct 2019 20:44:56 +0000 (20:44 +0000)]
gn build: Merge r375375

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375376 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoReverted r375254 as it has broken some build bots for a long time.
Vladimir Vereschaka [Sun, 20 Oct 2019 20:39:33 +0000 (20:39 +0000)]
Reverted r375254 as it has broken some build bots for a long time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375375 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] Fold uadd.sat(a, b) == 0 and usub.sat(a, b) == 0
Nikita Popov [Sun, 20 Oct 2019 20:19:42 +0000 (20:19 +0000)]
[InstCombine] Fold uadd.sat(a, b) == 0 and usub.sat(a, b) == 0

This adds folds for comparing uadd.sat/usub.sat with zero:

 * uadd.sat(a, b) == 0 => a == 0 && b == 0 => (a | b) == 0
 * usub.sat(a, b) == 0 => a <= b

And inverted forms for !=.

Differential Revision: https://reviews.llvm.org/D69224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375374 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix buildbot error in SIRegisterInfo.cpp.
Zinovy Nis [Sun, 20 Oct 2019 20:01:16 +0000 (20:01 +0000)]
Fix buildbot error in SIRegisterInfo.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375373 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] Add tests for uadd/sub.sat(a, b) == 0; NFC
Nikita Popov [Sun, 20 Oct 2019 19:50:31 +0000 (19:50 +0000)]
[InstCombine] Add tests for uadd/sub.sat(a, b) == 0; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375372 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] Shift amount reassociation in shifty sign bit test (PR43595)
Roman Lebedev [Sun, 20 Oct 2019 19:38:50 +0000 (19:38 +0000)]
[InstCombine] Shift amount reassociation in shifty sign bit test (PR43595)

Summary:
This problem consists of several parts:
* Basic sign bit extraction - `trunc? (?shr %x, (bitwidth(x)-1))`.
  This is trivial, and easy to do, we have a fold for it.
* Shift amount reassociation - if we have two identical shifts,
  and we can simplify-add their shift amounts together,
  then we likely can just perform them as a single shift.
  But this is finicky, has one-use restrictions,
  and shift opcodes must be identical.

But there is a super-pattern where both of these work together.
to produce sign bit test from two shifts + comparison.
We do indeed already handle this in most cases.
But since we get that fold transitively, it has one-use restrictions.
And what's worse, in this case the right-shifts aren't required to be
identical, and we can't handle that transitively:

If the total shift amount is bitwidth-1, only a sign bit will remain
in the output value. But if we look at this from the perspective of
two shifts, we can't fold - we can't possibly know what bit pattern
we'd produce via two shifts, it will be *some* kind of a mask
produced from original sign bit, but we just can't tell it's shape:
https://rise4fun.com/Alive/cM0 https://rise4fun.com/Alive/9IN

But it will *only* contain sign bit and zeros.
So from the perspective of sign bit test, we're good:
https://rise4fun.com/Alive/FRz https://rise4fun.com/Alive/qBU
Superb!

So the simplest solution is to extend `reassociateShiftAmtsOfTwoSameDirectionShifts()` to also have a
sudo-analysis mode that will ignore extra-uses, and will only check
whether a) those are two right shifts and b) they end up with bitwidth(x)-1
shift amount and return either the original value that we sign-checking,
or null.

This does not have any functionality change for
the existing `reassociateShiftAmtsOfTwoSameDirectionShifts()`.

All that being said, as disscussed in the review, this yet again
increases usage of instsimplify in instcombine as utility.
Some day that may need to be reevaluated.

https://bugs.llvm.org/show_bug.cgi?id=43595

Reviewers: spatel, efriedma, vsk

Reviewed By: spatel

Subscribers: xbolva00, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68930

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375371 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ConstantRange] makeGuaranteedNoWrapRegion(): `shl` support
Roman Lebedev [Sun, 20 Oct 2019 19:36:55 +0000 (19:36 +0000)]
[ConstantRange] makeGuaranteedNoWrapRegion(): `shl` support

Summary:
If all the shifts amount are already poison-producing,
then we can add more poison-producing flags ontop:
https://rise4fun.com/Alive/Ocwi

Otherwise, we should only consider the possible range of shift amts that don't result in poison.

For unsigned range not not overflow, we must not shift out any set bits,
and the actual limit for `x` can be computed by backtransforming
the maximal value we could ever get out of the `shl` - `-1` through
`lshr`. If the `x` is any larger than that then it will overflow.

Likewise for signed range, but just in signed domain..

This is based on the general idea outlined by @nikic in https://reviews.llvm.org/D68672#1714990

Reviewers: nikic, sanjoy

Reviewed By: nikic

Subscribers: hiraditya, llvm-commits, nikic

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375370 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ConstantRange] Optimize nowrap region test, remove redundant tests; NFC
Nikita Popov [Sun, 20 Oct 2019 18:59:14 +0000 (18:59 +0000)]
[ConstantRange] Optimize nowrap region test, remove redundant tests; NFC

Enumerate one less constant range in TestNoWrapRegionExhaustive,
which was unnecessary. This allows us to bump the bit count from
3 to 5 while keeping reasonable timing.

Drop four tests for multiply nowrap regions, as these cover subsets
of the exhaustive test. They do use a wider bitwidth, but I don't
think it's worthwhile to have them additionally now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375369 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Increase vcc liveness scan threshold
Matt Arsenault [Sun, 20 Oct 2019 17:44:17 +0000 (17:44 +0000)]
AMDGPU: Increase vcc liveness scan threshold

Avoids a test regression in a future patch. Also add debug printing on
this case, so I waste less time debugging folds in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375367 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Split flat offsets that don't fit in DAG
Matt Arsenault [Sun, 20 Oct 2019 17:34:44 +0000 (17:34 +0000)]
AMDGPU: Split flat offsets that don't fit in DAG

We handle it this way for some other address spaces.

Since r349196, SILoadStoreOptimizer has been trying to do this. This
is after SIFoldOperands runs, which can change the addressing
patterns. It's simpler to just split this earlier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375366 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Fix missing OPERAND_IMMEDIATE
Matt Arsenault [Sun, 20 Oct 2019 16:56:10 +0000 (16:56 +0000)]
AMDGPU: Fix missing OPERAND_IMMEDIATE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375365 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Add baseline tests for flat offset splitting
Matt Arsenault [Sun, 20 Oct 2019 16:33:21 +0000 (16:33 +0000)]
AMDGPU: Add baseline tests for flat offset splitting

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375364 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Don't re-get the subtarget
Matt Arsenault [Sun, 20 Oct 2019 16:26:26 +0000 (16:26 +0000)]
AMDGPU: Don't re-get the subtarget

It's already available in the class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375363 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[yaml2obj][obj2yaml] - Do not create a symbol table by default.
George Rimar [Sun, 20 Oct 2019 14:47:17 +0000 (14:47 +0000)]
[yaml2obj][obj2yaml] - Do not create a symbol table by default.

This patch tries to resolve problems faced in D68943
and uses some of the code written by Konrad Wilhelm Kleine
in that patch.

Previously, yaml2obj tool always created a .symtab section.
This patch changes that. With it we only create it when
have a "Symbols:" tag in the YAML document or when
we need to create it because it is used by another section(s).

obj2yaml follows the new behavior and does not print "Symbols:"
anymore when there is no symbol table.

Differential revision: https://reviews.llvm.org/D69041

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375361 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix minor warning in DWARFVerifier.
Zinovy Nis [Sun, 20 Oct 2019 07:55:50 +0000 (07:55 +0000)]
Fix minor warning in DWARFVerifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375357 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Don't error on calls to null or undef
Matt Arsenault [Sun, 20 Oct 2019 07:46:04 +0000 (07:46 +0000)]
AMDGPU: Don't error on calls to null or undef

Calls to constants should probably be generally handled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375356 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[SCEV] Simplify umin/max of zext and sext of the same value
Philip Reames [Sat, 19 Oct 2019 17:23:02 +0000 (17:23 +0000)]
[SCEV] Simplify umin/max of zext and sext of the same value

This is a common idiom which arises after induction variables are widened, and we have two or more exit conditions.  Interestingly, we don't have instcombine or instsimplify support for this either.

Differential Revision: https://reviews.llvm.org/D69006

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375349 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] Pulled out helper to decode target shuffle element sentinel values to 'Zeroable...
Simon Pilgrim [Sat, 19 Oct 2019 16:58:24 +0000 (16:58 +0000)]
[X86] Pulled out helper to decode target shuffle element sentinel values to 'Zeroable' known undef/zero bits. NFCI.

Renamed 'resolveTargetShuffleAndZeroables' to 'resolveTargetShuffleFromZeroables' to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375348 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2)
Sanjay Patel [Sat, 19 Oct 2019 16:57:02 +0000 (16:57 +0000)]
[TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2)

Provides a TLI hook to allow targets to relax the emission of shifts, thus enabling
codegen improvements on targets with no multiple shift instructions and cheap selects
or branches.

Contributes to a Fix for PR43559:
https://bugs.llvm.org/show_bug.cgi?id=43559

Patch by: @joanlluch (Joan LLuch)

Differential Revision: https://reviews.llvm.org/D69116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375347 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM] Add dependency on GlobalISel for unit tests to fix shared libs build
Nemanja Ivanovic [Sat, 19 Oct 2019 16:40:26 +0000 (16:40 +0000)]
[ARM] Add dependency on GlobalISel for unit tests to fix shared libs build

The unit test uses GlobalISel but the dependency is not listed in the
CMakeLists.txt file which causes failures in shared libs build with GCC.

This just adds the dependency.

Differential revision: https://reviews.llvm.org/D69064

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375346 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC
Sanjay Patel [Sat, 19 Oct 2019 16:29:32 +0000 (16:29 +0000)]
[MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC

Patch by: @joanlluch (Joan LLuch)

Differential Revision: https://reviews.llvm.org/D69099

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375345 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86][SSE] lowerV16I8Shuffle - tryToWidenViaDuplication - undef unpack args
Simon Pilgrim [Sat, 19 Oct 2019 13:18:02 +0000 (13:18 +0000)]
[X86][SSE] lowerV16I8Shuffle - tryToWidenViaDuplication - undef unpack args

tryToWidenViaDuplication lowers using the shuffle_v8i16(unpack_v16i8(shuffle_v8i16(x),shuffle_v8i16(x))) pattern, but the unpack only needs the even/odd 16i8 args if the original v16i8 shuffle mask references the even/odd elements - which isn't true for many extension style shuffles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375342 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86][SSE] LowerUINT_TO_FP_i64 - only use HADDPD for size/fast-hops
Simon Pilgrim [Sat, 19 Oct 2019 11:53:48 +0000 (11:53 +0000)]
[X86][SSE] LowerUINT_TO_FP_i64 - only use HADDPD for size/fast-hops

We were always generating a single source HADDPD, but really we should only do this if shouldUseHorizontalOp says its a good idea.

Differential Revision: https://reviews.llvm.org/D69175

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375341 91177308-0d34-0410-b5e6-96231b3b80d8