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granicus.if.org Git - llvm/log
Hans Wennborg [Wed, 24 Jun 2015 19:50:28 +0000 (19:50 +0000)]
Fix the VS2012 build after r240285.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240577
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Daniel Sanders [Mon, 22 Jun 2015 21:11:02 +0000 (21:11 +0000)]
Partially Merging r237790:
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r237790 | dsanders | 2015-05-20 14:19:19 +0100 (Wed, 20 May 2015) | 15 lines
[mips] Fix ehframe-indirect.ll test.
Summary:
-check-prefix replaces the default CHECK prefix rather than adding to it and
must be explicitly re-added.
Also added the N32 cases.
Reviewers: petarj
Reviewed By: petarj
Subscribers: tberghammer, llvm-commits
Differential Revision: http://reviews.llvm.org/D9668
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Merged all except the N32 cases which seem to require later patches that
are fine on the trunk but don't seem to work on the branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240333
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Tom Stellard [Mon, 22 Jun 2015 14:58:20 +0000 (14:58 +0000)]
Merging r238147:
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r238147 | thomas.stellard | 2015-05-25 12:15:54 -0400 (Mon, 25 May 2015) | 4 lines
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
The src and dst register cannot be the same on chips with 16 lds banks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240285
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Tom Stellard [Mon, 22 Jun 2015 14:58:18 +0000 (14:58 +0000)]
Merging r238146:
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r238146 | thomas.stellard | 2015-05-25 12:15:50 -0400 (Mon, 25 May 2015) | 6 lines
R600/SI: Use NAME rather than opName as the key to the MCOpcode tables
This lets us drop a parameter the opName parameter to the VINTRP
multiclass and makes it possible to create multiple VINTRP defs
with the same asm mnemonic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240284
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Tom Stellard [Mon, 22 Jun 2015 14:58:16 +0000 (14:58 +0000)]
Merging r237164:
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r237164 | thomas.stellard | 2015-05-12 14:59:17 -0400 (Tue, 12 May 2015) | 10 lines
R600/SI: Fix bug in VGPR spilling
AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which
caused the srsrc and soffset register to not be set correctly.
This commit replaces the switch statement with a SITargetInfo query
to make sure all spill instructions are covered.
Differential Revision: http://reviews.llvm.org/D9582
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240283
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Tom Stellard [Mon, 22 Jun 2015 14:58:12 +0000 (14:58 +0000)]
Merging r237152:
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r237152 | thomas.stellard | 2015-05-12 13:13:02 -0400 (Tue, 12 May 2015) | 20 lines
R600/SI: add pass to mark CF live ranges as non-spillable
Spilling can insert instructions almost anywhere, and this can mess
up control flow lowering in a multitude of ways, due to instruction
reordering. Let's sort this out the easy way: never spill registers
involved with control flow, i.e. saved EXEC masks.
Unfortunately, this does not work at all with optimizations disabled,
as the register allocator ignores spill weights. This should be
addressed in a future commit.
The test was reduced from the "stacks" shader of [1]. Some issues
trigger the machine verifier while another one is checked manually.
[1] http://madebyevan.com/webgl-path-tracing/
v2: only insert pass with optimizations enabled, merge test runs.
Patch by: Grigori Goronzy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240282
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Tom Stellard [Mon, 22 Jun 2015 14:58:09 +0000 (14:58 +0000)]
Daniel Sanders [Sun, 14 Jun 2015 15:45:45 +0000 (15:45 +0000)]
Merging r238751:
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r238751 | rafael | 2015-06-01 16:10:51 +0100 (Mon, 01 Jun 2015) | 3 lines
Fix relocation selection for foo-. on mips.
This handles only the 32 bit case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@239700
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Daniel Sanders [Sun, 14 Jun 2015 15:38:10 +0000 (15:38 +0000)]
Revert 239698 - Accidentally committed more than intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@239699
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Daniel Sanders [Sun, 14 Jun 2015 15:36:12 +0000 (15:36 +0000)]
Merging r238751:
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r238751 | rafael | 2015-06-01 16:10:51 +0100 (Mon, 01 Jun 2015) | 3 lines
Fix relocation selection for foo-. on mips.
This handles only the 32 bit case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@239698
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Tim Northover [Fri, 12 Jun 2015 15:57:35 +0000 (15:57 +0000)]
Merging r236457 and r236635:
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r236457 | tnorthover | 2015-05-04 13:41:51 -0700 (Mon, 04 May 2015) |
9 lines
CodeGen: match up correct insertvalue indices when assessing tail
calls.
When deciding whether a value comes from the aggregate or inserted
value of an insertvalue instruction, we compare the indices against
those of the location we're interested in. One of the lists needs
reversing because the input data is backwards (so that modifications
take place at the end of the SmallVector), but we were reversing both
before leading to incorrect results.
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r236635 | tnorthover | 2015-05-06 13:07:38 -0700 (Wed, 06 May 2015) |
12 lines
CodeGen: move over-zealous assert into actual if statement.
It's quite possible to encounter an insertvalue instruction that's
more deeply nested than the value we're looking for, but when that
happens we really mustn't compare beyond the end of the index array.
Since I couldn't see any guarantees about what comparisons std::equal
makes, we probably need to directly check the size beforehand. In
practice, I suspect most std::equal implementations would probably
bail early, which would be OK. But just in case...
rdar://
20834485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@239611
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Tom Stellard [Mon, 1 Jun 2015 14:30:22 +0000 (14:30 +0000)]
Bump version to 3.6.2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@238746
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Daniel Sanders [Fri, 15 May 2015 10:06:38 +0000 (10:06 +0000)]
[mips] Update release notes to account for revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@237433
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Daniel Sanders [Fri, 15 May 2015 10:05:22 +0000 (10:05 +0000)]
Revert r235869 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.
It introduced two regressions (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and
MultiSource/Applications/kimwitu++/kc) on 3 out of 23 cross-compilation
test-runs used by Mips for release validation.
The issue is that on 64-bit targets comparisons such as BEQ compare the whole
GPR64 but incorrectly tell the instruction selector that they operate on
GPR32's. This leads to the elimination of i32->i64 extensions that are actually
required by comparisons to work correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@237432
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Tom Stellard [Mon, 11 May 2015 19:46:44 +0000 (19:46 +0000)]
Merging r226124:
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r226124 | hans | 2015-01-14 23:36:20 -0500 (Wed, 14 Jan 2015) | 2 lines
utils/release/tag.sh: fix -revision vs. -rc check
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@237015
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Tom Stellard [Fri, 8 May 2015 14:13:47 +0000 (14:13 +0000)]
Merging r229413:
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r229413 | atrick | 2015-02-16 13:10:47 -0500 (Mon, 16 Feb 2015) | 16 lines
AArch64: Safely handle the incoming sret call argument.
This adds a safe interface to the machine independent InputArg struct
for accessing the index of the original (IR-level) argument. When a
non-native return type is lowered, we generate the hidden
machine-level sret argument on-the-fly. Before this fix, we were
representing this argument as OrigArgIndex == 0, which is an outright
lie. In particular this crashed in the AArch64 backend where we
actually try to access the type of the original argument.
Now we use a sentinel value for machine arguments that have no
original argument index. AArch64, ARM, Mips, and PPC now check for this
case before accessing the original argument.
Fixes <rdar://
19792160 > Null pointer assertion in AArch64TargetLowering
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236856
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Tom Stellard [Thu, 7 May 2015 22:09:33 +0000 (22:09 +0000)]
Merging r234977:
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r234977 | lhames | 2015-04-15 00:46:01 -0400 (Wed, 15 Apr 2015) | 5 lines
[RuntimeDyld] Add casts to make delta computation 64-bit.
Hopefully this will fix the i686/msvc build failure described at:
http://bb.pgr.jp/builders/ninja-clang-i686-msc18-R/builds/803
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236784
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Tom Stellard [Tue, 5 May 2015 14:43:00 +0000 (14:43 +0000)]
Merging r230564:
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r230564 | spatel | 2015-02-25 17:46:08 -0500 (Wed, 25 Feb 2015) | 8 lines
only propagate equality comparisons of FP values that we are certain are non-zero
This is a follow-on to r227491 which tightens the check for propagating FP
values. If a non-constant value happens to be a zero, we would hit the same
bug as before.
Bug noted and patch suggested by Eli Friedman.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236499
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Tom Stellard [Mon, 4 May 2015 19:50:17 +0000 (19:50 +0000)]
Merging r236307:
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r236307 | thomas.stellard | 2015-04-30 23:44:09 -0400 (Thu, 30 Apr 2015) | 4 lines
R600/SI: Add VCC as an implict def of SI_KILL
When SI_KILL has a register operand, its lowered form writes to vcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236452
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Tom Stellard [Mon, 4 May 2015 19:50:16 +0000 (19:50 +0000)]
Merging r236306:
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r236306 | thomas.stellard | 2015-04-30 23:44:08 -0400 (Thu, 30 Apr 2015) | 11 lines
R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass
This pass was generating 'Instruction does not dominate all uses!'
errors for programs which had loops with a condition variable that
depended on the result of a phi instruction from outside of the loop.
The pass was inserting new phi nodes outside of the loop which used values
defined inside the loop.
http://bugs.freedesktop.org/show_bug.cgi?id=90056
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236451
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Tom Stellard [Mon, 4 May 2015 19:50:14 +0000 (19:50 +0000)]
Merging r235662:
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r235662 | thomas.stellard | 2015-04-23 18:59:24 -0400 (Thu, 23 Apr 2015) | 2 lines
R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236450
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Tom Stellard [Mon, 4 May 2015 19:50:13 +0000 (19:50 +0000)]
Merging r235641:
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r235641 | thomas.stellard | 2015-04-23 16:32:01 -0400 (Thu, 23 Apr 2015) | 9 lines
R600/SI: Fix indirect addressing with a negative constant offset
When the base register index of the vector plus the constant offset
was less than zero, we were passing the wrong base register to the indirect
addressing instruction.
In this case, we need to set the base register to v0 and then add
the computed (negative) index to m0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236449
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Tom Stellard [Mon, 4 May 2015 19:50:11 +0000 (19:50 +0000)]
Merging r235524:
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r235524 | Matthew.Arsenault | 2015-04-22 13:10:44 -0400 (Wed, 22 Apr 2015) | 4 lines
R600: Fix always inline pass breaking noinline functions
No test since calls are not actually supported yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236448
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Tom Stellard [Mon, 4 May 2015 19:18:18 +0000 (19:18 +0000)]
GCOV: Fix ABI breakage from r236303
This effectively reverts the part of r236303, which added a new member
to the GCOVOptions and broke ABI compatibility with 3.6.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236445
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Daniel Sanders [Mon, 4 May 2015 11:39:04 +0000 (11:39 +0000)]
[mips] Added release notes for 3.6.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236417
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Tom Stellard [Sat, 2 May 2015 04:17:33 +0000 (04:17 +0000)]
Merging r227574:
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r227574 | geek4civic | 2015-01-30 08:01:19 -0500 (Fri, 30 Jan 2015) | 2 lines
[Cygming] Seek also chkstk_ms, or JIT fails with DLL builds. It is fixup for r227519.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236379
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Tom Stellard [Sat, 2 May 2015 04:17:29 +0000 (04:17 +0000)]
Merging r227519:
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r227519 | reid | 2015-01-29 18:58:04 -0500 (Thu, 29 Jan 2015) | 10 lines
x86: Fix large model calls to __chkstk for dynamic allocas
In the large code model, we now put __chkstk in %r11 before calling it.
Refactor the code so that we only do this once. Simplify things by using
__chkstk_ms instead of __chkstk on cygming. We already use that symbol
in the prolog emission, and it simplifies our logic.
Second half of PR18582.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236378
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Tom Stellard [Fri, 1 May 2015 02:43:16 +0000 (02:43 +0000)]
Merging r232443:
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r232443 | mail | 2015-03-16 20:18:51 -0400 (Mon, 16 Mar 2015) | 4 lines
llvm-cov: Warn instead of error if a .gcda has arcs from an exit block
Patch by Vanderson M. Rosario. Thanks!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236304
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Tom Stellard [Fri, 1 May 2015 02:43:13 +0000 (02:43 +0000)]
Merging r232438:
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r232438 | mail | 2015-03-16 19:52:03 -0400 (Mon, 16 Mar 2015) | 6 lines
GCOV: Make the exit block placement from r223193 optional
By default we want our gcov emission to stay 4.2 compatible, which
means we need to continue emit the exit block last by default. We add
an option to emit it before the body for users that need it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236303
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Tom Stellard [Fri, 1 May 2015 02:43:11 +0000 (02:43 +0000)]
Merging r227503:
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r227503 | reid | 2015-01-29 17:33:00 -0500 (Thu, 29 Jan 2015) | 11 lines
Update comments to use unreachable instead of llvm.trap, as implemented now
win64: Call __chkstk through a register with the large code model
Fixes half of PR18582. True dynamic allocas will still have a
CALL64pcrel32 which will fail.
Reviewers: majnemer
Differential Revision: http://reviews.llvm.org/D7267
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236302
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Tom Stellard [Thu, 30 Apr 2015 21:24:06 +0000 (21:24 +0000)]
Merging r231259:
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r231259 | marek.olsak | 2015-03-04 12:33:45 -0500 (Wed, 04 Mar 2015) | 4 lines
R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32
Required by OpenGL (ARB_gpu_shader5).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236263
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Daniel Sanders [Thu, 30 Apr 2015 09:21:49 +0000 (09:21 +0000)]
Merging r236099:
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r236099 | dsanders | 2015-04-29 13:28:58 +0100 (Wed, 29 Apr 2015) | 13 lines
[mips] Correct 128-bit shifts on 64-bit targets.
Summary:
The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now
accounts for both cases.
Reviewers: vkalintiris
Reviewed By: vkalintiris
Subscribers: llvm-commits, mohit.bhakkad, sagar
Differential Revision: http://reviews.llvm.org/D9337
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236215
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Pawel Bylica [Wed, 29 Apr 2015 16:05:29 +0000 (16:05 +0000)]
Correct syntax of getelementptr in regression test. NFC
Bonus: unused variable removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236116
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Daniel Sanders [Wed, 29 Apr 2015 15:29:14 +0000 (15:29 +0000)]
Attempt #2: Fix ABI compatibility with 3.6.0 by moving new virtual function to end of subclass. NFC
The previous attempt at fixing this only moved the problem to the subclass
vtable. We can safely move the function into the subclass so attempt to fix it
that way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236112
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Pawel Bylica [Wed, 29 Apr 2015 14:57:35 +0000 (14:57 +0000)]
Merge r232176: ConstantFold: Fix big shift constant folding
Constant folding for shift IR instructions ignores all bits above 32 of
second argument (shift amount).
Because of that, some undef results are not recognized and APInt can
raise an assert failure if second argument has more than 64 bits.
Patch by Paweł Bylica!
Differential Revision: http://reviews.llvm.org/D7701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236109
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Pawel Bylica [Wed, 29 Apr 2015 14:54:57 +0000 (14:54 +0000)]
Merge r231984: Handle big index in getelementptr instruction
CodeGen incorrectly ignores (assert from APInt) constant index bigger
than 2^64 in getelementptr instruction. This is a test and fix for that.
Patch by Paweł Bylica!
Reviewed By: rnk
Subscribers: majnemer, rnk, mcrosier, resistor, llvm-commits
Differential Revision: http://reviews.llvm.org/D8219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236108
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Daniel Sanders [Wed, 29 Apr 2015 09:58:25 +0000 (09:58 +0000)]
Fix ABI compatibility with 3.6.0 by moving new virtual function to end of class. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236094
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Tom Stellard [Wed, 29 Apr 2015 00:59:51 +0000 (00:59 +0000)]
Merging r234891:
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r234891 | thomas.stellard | 2015-04-14 10:36:45 -0400 (Tue, 14 Apr 2015) | 12 lines
R600/SI: Fix verifier error caused by SIAnnotateControlFlow
This pass will always try to insert llvm.SI.ifbreak intrinsics
in the same block that its conditional value is computed in. This is
a problem when conditions for breaks or continue are computed outside
of the loop, because the llvm.SI.ifbreak intrinsic ends up being inserted
outside of the loop.
This patch fixes this problem by inserting the llvm.SI.ifbreak
intrinsics in the loop header when the condition is computed outside
the loop.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236072
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Tom Stellard [Wed, 29 Apr 2015 00:59:49 +0000 (00:59 +0000)]
Merging r233080:
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r233080 | marek.olsak | 2015-03-24 09:40:38 -0400 (Tue, 24 Mar 2015) | 4 lines
R600/SI: Insert more NOPs after READLANE on VI, don't use NOPs on CI
This is a candidate for stable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236071
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Tom Stellard [Wed, 29 Apr 2015 00:59:47 +0000 (00:59 +0000)]
Merging r233075:
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r233075 | marek.olsak | 2015-03-24 09:40:08 -0400 (Tue, 24 Mar 2015) | 8 lines
R600/SI: Expand fract to floor, then only select V_FRACT on CI
V_FRACT is buggy on SI.
R600-specific code is left intact.
v2: drop the multiclass, use complex VOP3 patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236070
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Tom Stellard [Wed, 29 Apr 2015 00:59:42 +0000 (00:59 +0000)]
Merging r232957:
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r232957 | thomas.stellard | 2015-03-23 12:06:01 -0400 (Mon, 23 Mar 2015) | 5 lines
R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()
This function assumed that SMRD instructions always have immediate
offsets, which is not always the case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236069
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Tom Stellard [Wed, 29 Apr 2015 00:41:57 +0000 (00:41 +0000)]
Merging r234975:
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r234975 | lhames | 2015-04-14 23:39:22 -0400 (Tue, 14 Apr 2015) | 5 lines
[RuntimeDyld] Make sure we emit MachO __eh_frame and __gcc_except_tab sections,
even if there are no references to them in the code.
This allows exceptions thrown from JIT'd code to be caught by the JIT itself.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236068
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Tom Stellard [Wed, 29 Apr 2015 00:41:55 +0000 (00:41 +0000)]
Merging r233410:
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r233410 | ahmed.bougacha | 2015-03-27 16:35:49 -0400 (Fri, 27 Mar 2015) | 10 lines
[CodeGen] Don't attempt a tail-call with a non-forwarded explicit sret.
Tailcalls are only OK with forwarded sret pointers. With explicit sret,
one approximation is to check that the pointer isn't an Instruction, as
in that case it might point into some local memory (alloca). That's not
OK with tailcalls.
Explicit sret counterpart to r233409.
Differential Revison: http://reviews.llvm.org/D8510
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Tom Stellard [Wed, 29 Apr 2015 00:41:53 +0000 (00:41 +0000)]
Merging r233409:
------------------------------------------------------------------------
r233409 | ahmed.bougacha | 2015-03-27 16:28:30 -0400 (Fri, 27 Mar 2015) | 7 lines
[CodeGen] Don't attempt a tail-call with implicit sret.
Tailcalls are only OK with forwarded sret pointers. With sret demotion,
they're not, as we'd have a pointer into a soon-to-be-dead stack frame.
Differential Revison: http://reviews.llvm.org/D8510
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Tom Stellard [Wed, 29 Apr 2015 00:41:51 +0000 (00:41 +0000)]
Merging r232142:
------------------------------------------------------------------------
r232142 | Hao.Liu | 2015-03-13 01:15:23 -0400 (Fri, 13 Mar 2015) | 9 lines
[MachineCopyPropagation] Fix a bug causing incorrect removal for the instruction sequences as follows
%Q5_Q6<def> = COPY %Q2_Q3
%D5<def> =
%D3<def> =
%D3<def> = COPY %D6 // Incorrectly removed in MachineCopyPropagation
Using of %D3 results in incorrect result ...
Reviewed in http://reviews.llvm.org/D8242
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Tom Stellard [Wed, 29 Apr 2015 00:41:48 +0000 (00:41 +0000)]
MIPS: Fix test that uses 3.7 load syntax
This was broken by r235973.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236064
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Tom Stellard [Tue, 28 Apr 2015 21:23:06 +0000 (21:23 +0000)]
Merging r232797:
------------------------------------------------------------------------
r232797 | thomas.stellard | 2015-03-19 23:12:42 -0400 (Thu, 19 Mar 2015) | 2 lines
R600/SI: Add missing CHECK-LABEL lines to a test
------------------------------------------------------------------------
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Tom Stellard [Tue, 28 Apr 2015 21:23:04 +0000 (21:23 +0000)]
Merging r232386:
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r232386 | thomas.stellard | 2015-03-16 11:53:55 -0400 (Mon, 16 Mar 2015) | 8 lines
R600/SI: don't try min3/max3/med3 with f64
There are no opcodes for this. This also adds a test case.
v2: make test more robust
Patch by: Grigori Goronzy
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Tom Stellard [Tue, 28 Apr 2015 21:23:02 +0000 (21:23 +0000)]
Merging r231662:
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r231662 | thomas.stellard | 2015-03-09 12:03:39 -0400 (Mon, 09 Mar 2015) | 2 lines
R600/SI: Fix opcode for ds_read2_b64 and ds_read2st64_b64
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Tom Stellard [Tue, 28 Apr 2015 21:23:00 +0000 (21:23 +0000)]
Merging r231659:
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r231659 | marek.olsak | 2015-03-09 11:48:09 -0400 (Mon, 09 Mar 2015) | 4 lines
R600/SI: Limit SGPRs to 80 on Tonga and Iceland
This is a candidate for stable.
------------------------------------------------------------------------
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Tom Stellard [Tue, 28 Apr 2015 21:22:56 +0000 (21:22 +0000)]
Merging r231658:
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r231658 | marek.olsak | 2015-03-09 11:48:00 -0400 (Mon, 09 Mar 2015) | 2 lines
R600/SI: Fix getNumSGPRsAllowed for VI
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Tom Stellard [Tue, 28 Apr 2015 19:12:20 +0000 (19:12 +0000)]
Merging r230147:
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r230147 | Matthew.Arsenault | 2015-02-21 16:29:04 -0500 (Sat, 21 Feb 2015) | 2 lines
R600/SI: Don't crash when getting immediate operand size
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Tom Stellard [Tue, 28 Apr 2015 19:12:19 +0000 (19:12 +0000)]
Merging r230146:
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r230146 | Matthew.Arsenault | 2015-02-21 16:29:00 -0500 (Sat, 21 Feb 2015) | 2 lines
R600/SI: Fix mad*k definitions
------------------------------------------------------------------------
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Tom Stellard [Tue, 28 Apr 2015 19:12:16 +0000 (19:12 +0000)]
Merging r229752:
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r229752 | marek.olsak | 2015-02-18 17:12:45 -0500 (Wed, 18 Feb 2015) | 10 lines
R600/SI: Fix READLANE and WRITELANE lane select for VI
VOP2 declares vsrc1, but VOP3 declares src1.
We can't use the same "ins" if the operands have different names in VOP2
and VOP3 encodings.
This fixes a hang in geometry shaders which spill M0 on VI.
(BTW it doesn't look like M0 needs spilling and the spilling seems
duplicated 3 times)
------------------------------------------------------------------------
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Tom Stellard [Tue, 28 Apr 2015 19:12:14 +0000 (19:12 +0000)]
Merging r229751:
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r229751 | marek.olsak | 2015-02-18 17:12:41 -0500 (Wed, 18 Feb 2015) | 2 lines
R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_C
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Tom Stellard [Tue, 28 Apr 2015 19:12:12 +0000 (19:12 +0000)]
Merging r229750:
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r229750 | marek.olsak | 2015-02-18 17:12:37 -0500 (Wed, 18 Feb 2015) | 4 lines
R600/SI: Remove explicit VOP operand checking
This should be handled by the OperandType checking.
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Tom Stellard [Tue, 28 Apr 2015 19:12:11 +0000 (19:12 +0000)]
Merging r229507:
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r229507 | thomas.stellard | 2015-02-17 11:36:00 -0500 (Tue, 17 Feb 2015) | 2 lines
R600/SI: Extend private extload pattern to include zext loads
------------------------------------------------------------------------
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Tom Stellard [Tue, 28 Apr 2015 19:12:08 +0000 (19:12 +0000)]
Merging r229239:
------------------------------------------------------------------------
r229239 | Matthew.Arsenault | 2015-02-13 23:30:08 -0500 (Fri, 13 Feb 2015) | 4 lines
R600/SI: Implement correct f64 fdiv
This version passes the OpenCL conformance test.
------------------------------------------------------------------------
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Daniel Sanders [Tue, 28 Apr 2015 09:39:55 +0000 (09:39 +0000)]
Merging r232943:
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r232943 | petarj | 2015-03-23 12:28:13 +0000 (Mon, 23 Mar 2015) | 10 lines
Fix sign extension for MIPS64 in makeLibCall function
Fixing sign extension in makeLibCall for MIPS64. In MIPS64 architecture all
32 bit arguments (int, unsigned int, float 32 (soft float)) must be sign
extended. This fixes test "MultiSource/Applications/oggenc/".
Patch by Strahinja Petrovic.
Differential Revision: http://reviews.llvm.org/D7791
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Daniel Sanders [Tue, 28 Apr 2015 09:39:13 +0000 (09:39 +0000)]
Merging r228765:
------------------------------------------------------------------------
r228765 | petarj | 2015-02-10 23:30:14 +0000 (Tue, 10 Feb 2015) | 12 lines
Fix makeLibCall argument (signed) in SoftenFloatRes_XINT_TO_FP function
The isSigned argument of makeLibCall function was hard-coded to false
(unsigned). This caused zero extension on MIPS64 soft float.
As the result SingleSource/Benchmarks/Stanford/FloatMM test and
SingleSource/UnitTests/2005-07-17-INT-To-FP test failed.
The solution was to use the proper argument.
Patch by Strahinja Petrovic.
Differential Revision: http://reviews.llvm.org/D7292
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Daniel Sanders [Mon, 27 Apr 2015 15:07:42 +0000 (15:07 +0000)]
Merging r231237:
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r231237 | vkalintiris | 2015-03-04 12:10:18 +0000 (Wed, 04 Mar 2015) | 6 lines
[mips] Specify the correct value type when combining a CMovFP node.
This commit fixes a bug introduced in r230956 where we were creating
CMovFP_{T,F} nodes with multiple return value types (one for each operand).
With this change the return value type of the new node is the same as the
value type of the True/False operands of the original node.
------------------------------------------------------------------------
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Daniel Sanders [Mon, 27 Apr 2015 14:57:52 +0000 (14:57 +0000)]
Merging r230956:
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r230956 | vkalintiris | 2015-03-02 12:47:32 +0000 (Mon, 02 Mar 2015) | 10 lines
[mips] Optimize conditional moves where RHS is zero.
Summary:
When the RHS of a conditional move node is zero, we can utilize the $zero
register by inverting the conditional move instruction and by swapping the
order of its True/False operands.
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D7945
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Daniel Sanders [Mon, 27 Apr 2015 14:50:09 +0000 (14:50 +0000)]
Merging r230500:
------------------------------------------------------------------------
r230500 | vmedic | 2015-02-25 15:24:37 +0000 (Wed, 25 Feb 2015) | 1 line
[MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.
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Daniel Sanders [Mon, 27 Apr 2015 14:41:51 +0000 (14:41 +0000)]
Merging r228403:
------------------------------------------------------------------------
r228403 | dsanders | 2015-02-06 16:37:30 +0000 (Fri, 06 Feb 2015) | 2 lines
[mips] Fix FileCheck prefixes with whitespace between 'CHECK' and ':'
------------------------------------------------------------------------
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Daniel Sanders [Mon, 27 Apr 2015 14:31:46 +0000 (14:31 +0000)]
Merging r233904:
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r233904 | vkalintiris | 2015-04-02 11:14:54 +0100 (Thu, 02 Apr 2015) | 9 lines
[mips] Make sure that we don't adjust the stack pointer by zero amount.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8638
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Daniel Sanders [Mon, 27 Apr 2015 13:36:41 +0000 (13:36 +0000)]
Merging r232382:
------------------------------------------------------------------------
r232382 | petarj | 2015-03-16 15:01:09 +0000 (Mon, 16 Mar 2015) | 13 lines
[MIPS] Fix justify error for small structures
Fix justify error for small structures bigger than 32 bits in fixed
arguments for MIPS64 big endian. There was a problem when small structures
are passed as fixed arguments. The structures that are bigger than 32 bits
but smaller than 64 bits were not left justified properly on MIPS64 big
endian. This is fixed by shifting the value to make it left justified when
appropriate.
Patch by Aleksandar Beserminji.
Differential Revision: http://reviews.llvm.org/D8174
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Daniel Sanders [Mon, 27 Apr 2015 13:07:43 +0000 (13:07 +0000)]
Merging r230748:
------------------------------------------------------------------------
r230748 | tomatabacu | 2015-02-27 10:44:02 +0000 (Fri, 27 Feb 2015) | 11 lines
[mips] Remove redundant periods from -mattr=help descriptions for MIPS.
Summary: Also fixes an infringement of the 80-column limit rule.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7910
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Daniel Sanders [Mon, 27 Apr 2015 12:56:05 +0000 (12:56 +0000)]
Merging r230742:
------------------------------------------------------------------------
r230742 | vkalintiris | 2015-02-27 09:01:39 +0000 (Fri, 27 Feb 2015) | 12 lines
[mips] Account for constant-zero operands in ADDE nodes.
Summary:
We identify the cases where the operand to an ADDE node is a constant
zero. In such cases, we can avoid generating an extra ADDu instruction
disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r).
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7906
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Daniel Sanders [Mon, 27 Apr 2015 12:22:47 +0000 (12:22 +0000)]
Merging r230657:
------------------------------------------------------------------------
r230657 | petarj | 2015-02-26 18:35:15 +0000 (Thu, 26 Feb 2015) | 13 lines
Fix justify error for small structures in varargs for MIPS64BE
There was a problem when passing structures as variable arguments.
The structures smaller than 64 bit were not left justified on MIPS64
big endian. This is now fixed by shifting the value to make it left-
justified when appropriate.
This fixes the bug http://llvm.org/bugs/show_bug.cgi?id=21608
Patch by Aleksandar Beserminji.
Differential Revision: http://reviews.llvm.org/D7881
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Daniel Sanders [Mon, 27 Apr 2015 12:15:29 +0000 (12:15 +0000)]
Merging r230235:
------------------------------------------------------------------------
r230235 | dsanders | 2015-02-23 17:22:16 +0000 (Mon, 23 Feb 2015) | 16 lines
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.
Summary:
-mno-odd-spreg prohibits the use of odd-numbered single-precision floating
point registers. However, vector insert/extract was still using them when
manipulating the subregisters of an MSA register. Fixed this by ensuring
that insertion/extraction is only performed on even-numbered vector
registers when -mno-odd-spreg is given.
Reviewers: vmedic, sstankovic
Reviewed By: sstankovic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7672
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Daniel Sanders [Mon, 27 Apr 2015 12:08:26 +0000 (12:08 +0000)]
Merging r229675:
------------------------------------------------------------------------
r229675 | vkalintiris | 2015-02-18 14:57:05 +0000 (Wed, 18 Feb 2015) | 7 lines
[mips] Avoid redundant sign extension of the result of binary bitwise instructions.
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7581
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Daniel Sanders [Mon, 27 Apr 2015 11:59:49 +0000 (11:59 +0000)]
Merging r227430:
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r227430 | vmedic | 2015-01-29 11:33:41 +0000 (Thu, 29 Jan 2015) | 1 line
[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
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Daniel Sanders [Mon, 27 Apr 2015 10:29:59 +0000 (10:29 +0000)]
Merging r227084:
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r227084 | vmedic | 2015-01-26 10:33:43 +0000 (Mon, 26 Jan 2015) | 1 line
When disassembler meets compact jump instructions for r6 it crashes as the access to operands array is out of range. This patch removes dedicated decoder method that wrongly handles decoding of these instructions.
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Daniel Sanders [Mon, 27 Apr 2015 10:20:08 +0000 (10:20 +0000)]
Merging r227269:
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r227269 | petarj | 2015-01-27 23:30:18 +0000 (Tue, 27 Jan 2015) | 7 lines
[mips] Use __clear_cache builtin instead of cacheflush()
Use __clear_cache builtin instead of cacheflush() in
Unix Memory::InvalidateInstructionCache().
Differential Revision: http://reviews.llvm.org/D7198
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Daniel Sanders [Mon, 27 Apr 2015 09:44:39 +0000 (09:44 +0000)]
Merging r226905:
------------------------------------------------------------------------
r226905 | tomatabacu | 2015-01-23 10:40:19 +0000 (Fri, 23 Jan 2015) | 18 lines
[mips] Add new error message and improve testing for parsing the .module directive.
Summary:
We used to silently ignore any empty .module's and we used to give an error saying that we found
an "unexpected token at start of statement" when the value of the option wasn't an identifier (e.g. if it was a number).
We now give an error saying that we "expected .module option identifier" in both of those cases.
I also fixed the other tests in mips-abi-bad.s, which all seemed to be broken.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7095
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Daniel Sanders [Mon, 27 Apr 2015 09:42:44 +0000 (09:42 +0000)]
Merging r226652:
------------------------------------------------------------------------
r226652 | vmedic | 2015-01-21 10:47:36 +0000 (Wed, 21 Jan 2015) | 1 line
[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions.
------------------------------------------------------------------------
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Daniel Sanders [Mon, 27 Apr 2015 08:55:45 +0000 (08:55 +0000)]
Merging r226409:
------------------------------------------------------------------------
r226409 | dsanders | 2015-01-18 18:43:10 +0000 (Sun, 18 Jan 2015) | 2 lines
[mips] 'CHECK :' is not a valid check directive. Fixed.
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Daniel Sanders [Mon, 27 Apr 2015 08:53:54 +0000 (08:53 +0000)]
Merging r226408:
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r226408 | dsanders | 2015-01-18 18:38:36 +0000 (Sun, 18 Jan 2015) | 9 lines
[mips] Make whitespace in disassembler tests more consistent. NFC.
The tests for the ISA's should now be approximately diffable. That is, the
output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines
for instructions that were added/removed to/from MIPS-I by MIPS-II. This
doesn't work perfectly at the moment due to ordering differences but it
should be close.
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Daniel Sanders [Mon, 27 Apr 2015 08:52:15 +0000 (08:52 +0000)]
Merging r226407:
------------------------------------------------------------------------
r226407 | dsanders | 2015-01-18 18:21:19 +0000 (Sun, 18 Jan 2015) | 3 lines
[mips] Make whitespace of disassembler tests more consistent by removing blank lines. NFC.
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Daniel Sanders [Mon, 27 Apr 2015 08:51:28 +0000 (08:51 +0000)]
Merging r226166:
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r226166 | vmedic | 2015-01-15 14:18:12 +0000 (Thu, 15 Jan 2015) | 1 line
Add disassembler tests for mips64r6 platform. There are no functional changes.
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Daniel Sanders [Mon, 27 Apr 2015 08:50:58 +0000 (08:50 +0000)]
Merging r226165:
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r226165 | vmedic | 2015-01-15 14:11:38 +0000 (Thu, 15 Jan 2015) | 1 line
Add disassembler tests for mips32r6 platform. There are no functional changes.
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Daniel Sanders [Mon, 27 Apr 2015 08:50:30 +0000 (08:50 +0000)]
Merging r226164:
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r226164 | vmedic | 2015-01-15 14:06:34 +0000 (Thu, 15 Jan 2015) | 1 line
Add disassembler tests for mips64r2 platform. There are no functional changes.
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Daniel Sanders [Mon, 27 Apr 2015 08:49:48 +0000 (08:49 +0000)]
Merging r226151:
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r226151 | vmedic | 2015-01-15 08:50:20 +0000 (Thu, 15 Jan 2015) | 1 line
Add disassembler tests for mips64 platform. There are no functional changes.
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Tom Stellard [Fri, 24 Apr 2015 01:30:56 +0000 (01:30 +0000)]
Merging r229238:
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r229238 | Matthew.Arsenault | 2015-02-13 23:24:28 -0500 (Fri, 13 Feb 2015) | 2 lines
R600/SI: Use complex operand folding for div_scale
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Tom Stellard [Fri, 24 Apr 2015 01:30:54 +0000 (01:30 +0000)]
Merging r229236:
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r229236 | Matthew.Arsenault | 2015-02-13 23:22:00 -0500 (Fri, 13 Feb 2015) | 7 lines
R600/SI: Fix implicit vcc operand to v_div_fmas_*
This should allow finally fixing the f64 fdiv implementation.
Test is disabled for VI since there seems to be a problem with one
of the buffer load instructions on it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235685
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Tom Stellard [Fri, 24 Apr 2015 01:30:51 +0000 (01:30 +0000)]
Merging r229235:
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r229235 | Matthew.Arsenault | 2015-02-13 23:03:18 -0500 (Fri, 13 Feb 2015) | 2 lines
R600/SI: Fix schedule model for v_div_scale_{f32|f64}
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235684
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Tom Stellard [Fri, 24 Apr 2015 01:30:49 +0000 (01:30 +0000)]
Merging r229234:
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r229234 | Matthew.Arsenault | 2015-02-13 22:54:32 -0500 (Fri, 13 Feb 2015) | 2 lines
R600/SI: Really fix size of VReg_1
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235683
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Tom Stellard [Fri, 24 Apr 2015 01:05:03 +0000 (01:05 +0000)]
Merging r229230:
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r229230 | Matthew.Arsenault | 2015-02-13 22:40:35 -0500 (Fri, 13 Feb 2015) | 4 lines
R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}
This apparently got lost in the VI changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235678
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Tom Stellard [Thu, 23 Apr 2015 19:14:45 +0000 (19:14 +0000)]
Merging r229228:
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r229228 | Matthew.Arsenault | 2015-02-13 22:02:23 -0500 (Fri, 13 Feb 2015) | 2 lines
R600/SI: Fix VOP3b encoding on VI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235625
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Tom Stellard [Thu, 23 Apr 2015 19:14:43 +0000 (19:14 +0000)]
Merging r229227:
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r229227 | Matthew.Arsenault | 2015-02-13 21:55:57 -0500 (Fri, 13 Feb 2015) | 2 lines
R600/SI: Fix phys reg copies in SIFoldOperands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235624
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Tom Stellard [Thu, 23 Apr 2015 19:14:42 +0000 (19:14 +0000)]
Merging r229226:
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r229226 | Matthew.Arsenault | 2015-02-13 21:55:56 -0500 (Fri, 13 Feb 2015) | 5 lines
R600/SI: Fix copies from SGPR to VCC
This shows up without optimizations when vcc is required
to be used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235623
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Tom Stellard [Thu, 23 Apr 2015 19:14:40 +0000 (19:14 +0000)]
Merging r229225:
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r229225 | Matthew.Arsenault | 2015-02-13 21:55:54 -0500 (Fri, 13 Feb 2015) | 4 lines
R600/SI: Add hack to copy from a VGPR to VCC
This hopefully should be fixed when VReg_1 is removed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235622
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Tom Stellard [Thu, 23 Apr 2015 19:14:38 +0000 (19:14 +0000)]
Merging r229223:
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r229223 | Matthew.Arsenault | 2015-02-13 21:51:44 -0500 (Fri, 13 Feb 2015) | 5 lines
R600/SI: Fix size of VReg_1
This is really a 32-bit register, if we try to check the size of it,
we want 32-bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235621
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Tom Stellard [Wed, 22 Apr 2015 21:13:11 +0000 (21:13 +0000)]
Merging r228848:
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r228848 | thomas.stellard | 2015-02-11 12:11:48 -0500 (Wed, 11 Feb 2015) | 2 lines
R600/SI: Fix -march in test
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235550
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Tom Stellard [Wed, 22 Apr 2015 21:13:10 +0000 (21:13 +0000)]
Merging r228374:
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r228374 | michel.daenzer | 2015-02-05 21:51:29 -0500 (Thu, 05 Feb 2015) | 4 lines
R600/SI: Amend a test to ensure WQM is enabled for LDS in pixel shaders
Reviewed-by: Tom Stellard <tom@stellard.net>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235549
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Tom Stellard [Wed, 22 Apr 2015 21:13:09 +0000 (21:13 +0000)]
Merging r228373:
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r228373 | michel.daenzer | 2015-02-05 21:51:25 -0500 (Thu, 05 Feb 2015) | 8 lines
R600/SI: Don't enable WQM for V_INTERP_* instructions v2
Doesn't seem necessary anymore. I think this was mostly compensating for
not enabling WQM for texture sampling instructions.
v2: Add test coverage
Reviewed-by: Tom Stellard <tom@stellard.net>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235548
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Tom Stellard [Wed, 22 Apr 2015 21:13:07 +0000 (21:13 +0000)]
Merging r228372:
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r228372 | michel.daenzer | 2015-02-05 21:51:20 -0500 (Thu, 05 Feb 2015) | 12 lines
R600/SI: Also enable WQM for image opcodes which calculate LOD v3
If whole quad mode isn't enabled for these, the level of detail is
calculated incorrectly for pixels along diagonal triangle edges, causing
artifacts.
v2: Use a TSFlag instead of lots of switch cases
v3: Add test coverage
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642
Reviewed-by: Tom Stellard <tom@stellard.net>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235547
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Tom Stellard [Wed, 22 Apr 2015 21:13:04 +0000 (21:13 +0000)]
Merging r228273:
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r228273 | Matthew.Arsenault | 2015-02-05 01:05:13 -0500 (Thu, 05 Feb 2015) | 2 lines
R600/SI: Fix i64 truncate to i1
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235546
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Tom Stellard [Mon, 20 Apr 2015 20:05:00 +0000 (20:05 +0000)]
Merging r228190:
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r228190 | thomas.stellard | 2015-02-04 15:49:52 -0500 (Wed, 04 Feb 2015) | 2 lines
R600/SI: Expand misaligned 16-bit memory accesses
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235340
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Tom Stellard [Mon, 20 Apr 2015 20:04:59 +0000 (20:04 +0000)]
Merging r228189:
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r228189 | thomas.stellard | 2015-02-04 15:49:51 -0500 (Wed, 04 Feb 2015) | 9 lines
R600/SI: Make more store operations legal
v2i32, i32, trunc i32 to i16, and truc i32 to i8 stores are legal for
all address spaces. We had marked them as custom in order to lower
them for the private address space, but this is no longer necessary.
This enables lowering of misaligned stores of these types in the
DAGLegalizer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235339
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