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5 years agoRecommit "[CommandLine] Remove OptionCategory and SubCommand caches from the Option...
Don Hinton [Wed, 10 Jul 2019 17:57:05 +0000 (17:57 +0000)]
Recommit "[CommandLine] Remove OptionCategory and SubCommand caches from the Option class."

Previously reverted in 364141 due to buildbot breakage, and fixed here
by making GeneralCategory global a ManagedStatic.

Summary:
This change processes `OptionCategory`s and `SubCommand`s as they
are seen instead of caching them in the Option class and processing
them later.  Doing so simplifies the work needed to be done by the Global
parser and significantly reduces the size of the Option class to a mere 64
bytes.

Removing  the `OptionCategory` cache saved 24 bytes, and removing
the `SubCommand` cache saved an additional 48 bytes, for a total of a
72 byte reduction.

Reviewed By: serge-sans-paille

Tags: #llvm, #clang

Differential Revision: https://reviews.llvm.org/D62105

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365675 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] EltsFromConsecutiveLoads - clean up element size calcs. NFCI.
Simon Pilgrim [Wed, 10 Jul 2019 17:49:27 +0000 (17:49 +0000)]
[X86] EltsFromConsecutiveLoads - clean up element size calcs. NFCI.

Determine the element/load size calculations earlier and assert that they are whole bytes in size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365674 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[LoopRotate + MemorySSA] Keep an <instruction-cloned instruction> map.
Alina Sbirlea [Wed, 10 Jul 2019 17:36:56 +0000 (17:36 +0000)]
[LoopRotate + MemorySSA] Keep an <instruction-cloned instruction> map.

Summary:
The map kept in loop rotate is used for instruction remapping, in order
to simplify the clones of instructions. Thus, if an instruction can be
simplified, its simplified value is placed in the map, even when the
clone is added to the IR. MemorySSA in contrast needs to know about that
clone, so it can add an access for it.
To resolve this: keep a different map for MemorySSA.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365672 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ORC] Add custom IR compiler configuration to LLJITBuilder to enable obj caches.
Lang Hames [Wed, 10 Jul 2019 17:24:24 +0000 (17:24 +0000)]
[ORC] Add custom IR compiler configuration to LLJITBuilder to enable obj caches.

LLJITBuilder now has a setCompileFunctionCreator method which can be used to
construct a CompileFunction for the LLJIT instance being created. The motivating
use-case for this is supporting ObjectCaches, which can now be set up at
compile-function construction time. To demonstrate this an example project,
LLJITWithObjectCache, is included.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365671 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] Regenerate tests. NFCI.
Simon Pilgrim [Wed, 10 Jul 2019 17:22:31 +0000 (17:22 +0000)]
[X86] Regenerate tests. NFCI.

Hasn't been regenerated since the update script could merge 32/64-bit checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365670 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] Add tests for an alternative sequence for _mm_storel_pi/_mm_storeh_pi intrinsic...
Craig Topper [Wed, 10 Jul 2019 17:11:18 +0000 (17:11 +0000)]
[X86] Add tests for an alternative sequence for _mm_storel_pi/_mm_storeh_pi intrinsics. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365667 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[TargetLowering] support BlockAddress as "i" inline asm constraint
Nick Desaulniers [Wed, 10 Jul 2019 17:08:25 +0000 (17:08 +0000)]
[TargetLowering] support BlockAddress as "i" inline asm constraint

Summary:
This allows passing address of labels to inline assembly "i" input
constraints.

Fixes pr/42502.

Reviewers: ostannard

Reviewed By: ostannard

Subscribers: void, echristo, nathanchance, ostannard, javed.absar, hiraditya, llvm-commits, srhines

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365664 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC][InstCombine] Fixup some tests in just-added "omit mask before left-shift" tests
Roman Lebedev [Wed, 10 Jul 2019 16:54:13 +0000 (16:54 +0000)]
[NFC][InstCombine] Fixup some tests in just-added "omit mask before left-shift" tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365663 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMC: AArch64: Add support for pg_hi21_nc relocation specifier.
Peter Collingbourne [Wed, 10 Jul 2019 16:36:46 +0000 (16:36 +0000)]
MC: AArch64: Add support for pg_hi21_nc relocation specifier.

Differential Revision: https://reviews.llvm.org/D64455

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365661 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[CodeExtractor] Fix sinking of allocas with multiple bitcast uses (PR42451)
Vedant Kumar [Wed, 10 Jul 2019 16:32:20 +0000 (16:32 +0000)]
[CodeExtractor] Fix sinking of allocas with multiple bitcast uses (PR42451)

An alloca which can be sunk into the extraction region may have more
than one bitcast use. Move these uses along with the alloca to prevent
use-before-def.

Testing: check-llvm, stage2 build of clang

Fixes llvm.org/PR42451.

Differential Revision: https://reviews.llvm.org/D64463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365660 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[CodeExtractor] Simplify findAllocas, NFC
Vedant Kumar [Wed, 10 Jul 2019 16:32:16 +0000 (16:32 +0000)]
[CodeExtractor] Simplify findAllocas, NFC

Split getLifetimeMarkers out into its own method and have it return a
struct.

Differential Revision: https://reviews.llvm.org/D64467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365659 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoGlobalISel: Legalization for G_FMINNUM/G_FMAXNUM
Matt Arsenault [Wed, 10 Jul 2019 16:31:19 +0000 (16:31 +0000)]
GlobalISel: Legalization for G_FMINNUM/G_FMAXNUM

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365658 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoGlobalISel: Define the full family of FP min/max instructions
Matt Arsenault [Wed, 10 Jul 2019 16:31:15 +0000 (16:31 +0000)]
GlobalISel: Define the full family of FP min/max instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365657 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] EltsFromConsecutiveLoads - remove duplicate check for element size. NFCI.
Simon Pilgrim [Wed, 10 Jul 2019 16:22:31 +0000 (16:22 +0000)]
[X86] EltsFromConsecutiveLoads - remove duplicate check for element size. NFCI.

We've already checked that each element is the correct contributory size for VT when we inspect the elements for Undef/Zero/Load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365656 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] EltsFromConsecutiveLoads - ensure element reg/store sizes are the same size...
Simon Pilgrim [Wed, 10 Jul 2019 16:14:26 +0000 (16:14 +0000)]
[X86] EltsFromConsecutiveLoads - ensure element reg/store sizes are the same size. NFCI.

This renames the type so it doesn't sound like its based off the load size - as we're moving towards supporting combining loads of different sizes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365655 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Serialize mode from MachineFunctionInfo
Matt Arsenault [Wed, 10 Jul 2019 16:09:26 +0000 (16:09 +0000)]
AMDGPU: Serialize mode from MachineFunctionInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365653 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[PatternMatch] Generalize m_SpecificInt_ULT() to take ICmpInst::Predicate
Roman Lebedev [Wed, 10 Jul 2019 16:07:35 +0000 (16:07 +0000)]
[PatternMatch] Generalize m_SpecificInt_ULT() to take ICmpInst::Predicate

As discussed in the original review, this may be useful,
so let's just do it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365652 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Remarks] Add cl::Hidden to -remarks-yaml-string-table
Francis Visoiu Mistrih [Wed, 10 Jul 2019 15:46:36 +0000 (15:46 +0000)]
[Remarks] Add cl::Hidden to -remarks-yaml-string-table

It was showing up in a lot of unrelated tools.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365647 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agodocs/GithubMove.rst: Remove obsolete information
Tom Stellard [Wed, 10 Jul 2019 15:39:37 +0000 (15:39 +0000)]
docs/GithubMove.rst: Remove obsolete information

Summary:
Remove references to the multirepo and update the document to
reflect the current state of the github repository.

Reviewers: mehdi_amini, jyknight

Subscribers: jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58420

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365645 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[FileCheck] Use bool operator to test Expected
Thomas Preud'homme [Wed, 10 Jul 2019 15:31:19 +0000 (15:31 +0000)]
[FileCheck] Use bool operator to test Expected

Use bool() consistently to get boolean value of Error, Optional and
Expected types in EXPECT calls. While static_cast is used in all cases
but one, bool provides more clarity and makes more sense as a new
default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365644 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC][InstCombine] Redundant masking before left-shift (PR42563)
Roman Lebedev [Wed, 10 Jul 2019 15:08:06 +0000 (15:08 +0000)]
[NFC][InstCombine] Redundant masking before left-shift (PR42563)

alive proofs:
a,b:     https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49

Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.

Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.

For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.

https://bugs.llvm.org/show_bug.cgi?id=42563

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365641 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32
Jay Foad [Wed, 10 Jul 2019 14:53:47 +0000 (14:53 +0000)]
[AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32

Summary:
D59191 added support for these modifiers in the assembler and
disassembler. This patch just teaches instruction selection that it can
use them.

Reviewers: arsenm, tstellar

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64497

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365640 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] pow(C,x) -> exp2(log2(C)*x)
David Bolvansky [Wed, 10 Jul 2019 14:43:27 +0000 (14:43 +0000)]
[InstCombine] pow(C,x) -> exp2(log2(C)*x)

Summary:
Transform
pow(C,x)

To
exp2(log2(C)*x)

if C > 0, C != inf, C != NaN (and C is not power of 2, since we have some fold for such case already).

log(C) is folded by the compiler and exp2 is much faster to compute than pow.

Reviewers: spatel, efriedma, evandro

Reviewed By: evandro

Subscribers: lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64099

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365637 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InferFunctionAttrs] add/adjust tests for dereferenceable; NFC
Sanjay Patel [Wed, 10 Jul 2019 14:41:47 +0000 (14:41 +0000)]
[InferFunctionAttrs] add/adjust tests for dereferenceable; NFC

Based on review comments for D64258.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365636 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agogn build: Merge r365585
Nico Weber [Wed, 10 Jul 2019 14:05:13 +0000 (14:05 +0000)]
gn build: Merge r365585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365633 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[docs][llvm-symbolizer] Fix grammar
James Henderson [Wed, 10 Jul 2019 13:40:45 +0000 (13:40 +0000)]
[docs][llvm-symbolizer] Fix grammar

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365630 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] EltsFromConsecutiveLoads - cleanup Zero/Undef/Load element collection. NFCI.
Simon Pilgrim [Wed, 10 Jul 2019 13:28:13 +0000 (13:28 +0000)]
[X86] EltsFromConsecutiveLoads - cleanup Zero/Undef/Load element collection. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365628 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MIPS GlobalISel] Select float and double phi
Petar Avramovic [Wed, 10 Jul 2019 13:18:13 +0000 (13:18 +0000)]
[MIPS GlobalISel] Select float and double phi

Select float and double phi for MIPS32.

Differential Revision: https://reviews.llvm.org/D64420

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365627 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[MIPS GlobalISel] Select float and double load and store
Petar Avramovic [Wed, 10 Jul 2019 12:55:21 +0000 (12:55 +0000)]
[MIPS GlobalISel] Select float and double load and store

Select float and double load and store for MIPS32.

Differential Revision: https://reviews.llvm.org/D64419

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365626 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[FileCheck] Simplify numeric variable interface
Thomas Preud'homme [Wed, 10 Jul 2019 12:49:28 +0000 (12:49 +0000)]
[FileCheck] Simplify numeric variable interface

Summary:
This patch simplifies 2 aspects in the FileCheckNumericVariable code.

First, setValue() method is turned into a void function since being
called only on undefined variable is an invariant and is now asserted
rather than returned. This remove the assert from the callers.

Second, clearValue() method is also turned into a void function since
the only caller does not check its return value since it may be trying
to clear the value of variable that is already cleared without this
being noteworthy.

Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk

Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64231

llvm-svn: 365249

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365625 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[FileCheck] Fix @LINE value after match failure
Thomas Preud'homme [Wed, 10 Jul 2019 12:49:17 +0000 (12:49 +0000)]
[FileCheck] Fix @LINE value after match failure

Summary:
The value of the FileCheckNumericVariable class instance representing
the @LINE numeric variable is set and cleared respectively before and
after substitutions are made, if any. However, when a substitution
fails, the value is not cleared. This causes the next substitution of
@LINE later on to give the wrong value since setValue is a nop if the
value is already set. This is what caused failures after commit r365249.

Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk

Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64449

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365624 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC][ARM] Convert lambdas to static helpers
Sam Parker [Wed, 10 Jul 2019 12:29:43 +0000 (12:29 +0000)]
[NFC][ARM] Convert lambdas to static helpers

Break up and convert some of the lambdas in ARMLowOverheadLoops into
static functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365623 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] EltsFromConsecutiveLoads - LDBase is non-null. NFCI.
Simon Pilgrim [Wed, 10 Jul 2019 12:22:59 +0000 (12:22 +0000)]
[X86] EltsFromConsecutiveLoads - LDBase is non-null. NFCI.

Don't bother checking for LDBase != null - it should be (and we assert that it is).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365622 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[DAGCombine] visitINSERT_SUBVECTOR - use uint64_t subvector index. NFCI.
Simon Pilgrim [Wed, 10 Jul 2019 12:21:35 +0000 (12:21 +0000)]
[DAGCombine] visitINSERT_SUBVECTOR - use uint64_t subvector index. NFCI.

Keep the uint64_t type from getZExtValue() to stop truncation/extension overflow warnings in MSVC in subvector index math.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365621 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] EltsFromConsecutiveLoads - store Loads on a per-element basis. NFCI.
Simon Pilgrim [Wed, 10 Jul 2019 11:26:57 +0000 (11:26 +0000)]
[X86] EltsFromConsecutiveLoads - store Loads on a per-element basis. NFCI.

Cache the LoadSDNode nodes so we can easily map to/from the element index instead of packing them together - this will be useful for future patches for PR16739 etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365620 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ELF] Loose a condition for relocation with a symbol
Nikola Prica [Wed, 10 Jul 2019 11:17:48 +0000 (11:17 +0000)]
[ELF] Loose a condition for relocation with a symbol

Deleted code was introduced as a work around for a bug in the gold linker
(http://sourceware.org/PR16794). Test case that was given as a reason for
this part of code, the one on previous link, now works for the gold.
This condition is too strict and when a code is compiled with debug info
it forces generation of numerous relocations with symbol for architectures
that do not have relocation addend.

Reviewers: arsenm, espindola

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D64327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365618 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support
Simon Pilgrim [Wed, 10 Jul 2019 10:46:36 +0000 (10:46 +0000)]
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support

This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it.

Another step towards partial vector loads......

Differential Revision: https://reviews.llvm.org/D64205

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365614 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix const/non-const lambda return type warning. NFCI.
Simon Pilgrim [Wed, 10 Jul 2019 10:45:09 +0000 (10:45 +0000)]
Fix const/non-const lambda return type warning. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365613 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
Simon Pilgrim [Wed, 10 Jul 2019 10:34:44 +0000 (10:34 +0000)]
Fix "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365612 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[SimpleLoopUnswitch] Don't consider unswitching `switch` insructions with one unique...
Serguei Katkov [Wed, 10 Jul 2019 10:25:22 +0000 (10:25 +0000)]
[SimpleLoopUnswitch] Don't consider unswitching `switch` insructions with one unique successor

Only instructions with two or more unique successors should be considered for unswitching.

Patch Author: Daniil Suchkov.

Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D64404

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365611 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present
Mikhail Maltsev [Wed, 10 Jul 2019 08:59:17 +0000 (08:59 +0000)]
[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present

Summary:
Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.

Patch by Momchil Velikov.

Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen

Reviewed By: dmgreen

Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365604 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[docs][llvm-dwarfdump] Normalise some wording
James Henderson [Wed, 10 Jul 2019 08:56:13 +0000 (08:56 +0000)]
[docs][llvm-dwarfdump] Normalise some wording

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365603 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[test/Object/nm-trivial-object.test] - Remove 4 precompiled binaries.
George Rimar [Wed, 10 Jul 2019 08:40:11 +0000 (08:40 +0000)]
[test/Object/nm-trivial-object.test] - Remove 4 precompiled binaries.

This converts 5 precompiled binaries to YAMLs,
removes 4 from inputs and performs a cleanup.

Differential revision: https://reviews.llvm.org/D64246

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365601 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[SimpleLoopUnswitch] Add a test case exposing a bug
Serguei Katkov [Wed, 10 Jul 2019 08:25:48 +0000 (08:25 +0000)]
[SimpleLoopUnswitch] Add a test case exposing a bug

This test exposes a bug in SimpleLoopUnswitch that leads to a crash on
assert(SuccessorsCount > 1 && "Cannot unswitch a condition without multiple distinct successors!");
when SimpleLoopUnswitch considers unswitching of a loop by a switch with one successor.

Fix will be submitted soon.

Patch Author: Daniil Suchkov.

Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D64403

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365600 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoSilence gcc warning by adding parentheses to condition [NFC]
Mikael Holmen [Wed, 10 Jul 2019 06:18:03 +0000 (06:18 +0000)]
Silence gcc warning by adding parentheses to condition [NFC]

Without this gcc 7.4.0 complains with

  ../include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h:457:54: error: suggest parentheses around '&&' within '||' [-Werror=parentheses]
                    isArtifactCast(TmpDef->getOpcode()) &&
                    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
                        "Expecting copy or artifact cast here");
                        ~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365597 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix modular build issues caused by BitCodes.h
Kristina Brooks [Wed, 10 Jul 2019 03:52:31 +0000 (03:52 +0000)]
Fix modular build issues caused by BitCodes.h

Consolidate llvm::BWH_* statics into an enum to fix
module build issues. This fixes the LLVM_Bitcode module,
getting rid of -Wmodules-ambiguous-internal-linkage.

Differential Revision: https://reviews.llvm.org/D64469

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365594 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] Limit getTargetConstantFromNode to only work on NormalLoads not extending loads.
Craig Topper [Wed, 10 Jul 2019 00:40:01 +0000 (00:40 +0000)]
[X86] Limit getTargetConstantFromNode to only work on NormalLoads not extending loads.

This seems to fix a failure reported by Jordan Rupprecht, but we
don't have a reduced test case yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365589 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Support] Move llvm::MemoryBuffer to sys::fs::file_t
Reid Kleckner [Wed, 10 Jul 2019 00:34:13 +0000 (00:34 +0000)]
[Support] Move llvm::MemoryBuffer to sys::fs::file_t

Summary:
On Windows, Posix integer file descriptors are a compatibility layer
over native file handles provided by the C runtime. There is a hard
limit on the maximum number of file descriptors that a process can open,
and the limit is 8192. LLD typically doesn't run into this limit because
it opens input files, maps them into memory, and then immediately closes
the file descriptor. This prevents it from running out of FDs.

For various reasons, I'd like to open handles to every input file and
keep them open during linking. That requires migrating MemoryBuffer over
to taking open native file handles instead of integer FDs.

Reviewers: aganea, Bigcheese

Reviewed By: aganea

Subscribers: smeenai, silvas, mehdi_amini, hiraditya, steven_wu, dexonsmith, dang, llvm-commits, zturner

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63453

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365588 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU/GlobalISel: Add support for wide loads >= 256-bits
Tom Stellard [Wed, 10 Jul 2019 00:22:41 +0000 (00:22 +0000)]
AMDGPU/GlobalISel: Add support for wide loads >= 256-bits

Summary:
This adds support for the most commonly used wide load types:
<8xi32>, <16xi32>, <4xi64>, and <8xi64>

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57399

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365586 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoGlobalISel: Implement lower for G_FCOPYSIGN
Matt Arsenault [Tue, 9 Jul 2019 23:34:29 +0000 (23:34 +0000)]
GlobalISel: Implement lower for G_FCOPYSIGN

In SelectionDAG AMDGPU treated these as legal, but this was mostly
because the bitcasts required for FP types were painful. Theoretically
the bitpattern should eventually match to bfi, so don't bother trying
to get the patterns to import.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365583 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Bitcode] Explicitly include Bitstream/BitCodes.h and BitstreamWriter.h
Francis Visoiu Mistrih [Tue, 9 Jul 2019 23:20:01 +0000 (23:20 +0000)]
[Bitcode] Explicitly include Bitstream/BitCodes.h and BitstreamWriter.h

This fixes a modules issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365580 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[docs][Remarks] Add documentation for remarks in LLVM
Francis Visoiu Mistrih [Tue, 9 Jul 2019 23:16:59 +0000 (23:16 +0000)]
[docs][Remarks] Add documentation for remarks in LLVM

This adds documentation that describes remarks in LLVM.

It aims at explaining what remarks are, how to enable them, and what
users can do with the different modes.

It lists all the available flags in LLVM (excluding clang), and
describes the expected YAML structure as well as the tools that support
the YAML format today.

Differential Revision: https://reviews.llvm.org/D64355

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365578 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] Don't form extloads in combineExtInVec unless the load extension is legal.
Craig Topper [Tue, 9 Jul 2019 23:05:54 +0000 (23:05 +0000)]
[X86] Don't form extloads in combineExtInVec unless the load extension is legal.

This should prevent doing this on pre-sse4.1 targets or for 256
bit vectors without avx2.

I don't know of a failure from this. Op legalization will probably
take care of, but seemed better to be safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365577 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR
Matt Arsenault [Tue, 9 Jul 2019 22:48:04 +0000 (22:48 +0000)]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365575 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AMDGPU] gfx908 v_pk_fmac_f16 support
Stanislav Mekhanoshin [Tue, 9 Jul 2019 22:42:24 +0000 (22:42 +0000)]
[AMDGPU] gfx908 v_pk_fmac_f16 support

Differential Revision: https://reviews.llvm.org/D64433

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365573 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agogn build: Merge r365536.
Peter Collingbourne [Tue, 9 Jul 2019 22:37:51 +0000 (22:37 +0000)]
gn build: Merge r365536.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365572 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agogn build: Merge r365532.
Peter Collingbourne [Tue, 9 Jul 2019 22:37:41 +0000 (22:37 +0000)]
gn build: Merge r365532.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365571 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agogn build: Merge r365541.
Peter Collingbourne [Tue, 9 Jul 2019 22:37:25 +0000 (22:37 +0000)]
gn build: Merge r365541.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365570 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agogn build: Merge r365531.
Peter Collingbourne [Tue, 9 Jul 2019 22:37:09 +0000 (22:37 +0000)]
gn build: Merge r365531.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365569 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAdd lldb type unit support to the release notes
Pavel Labath [Tue, 9 Jul 2019 22:36:43 +0000 (22:36 +0000)]
Add lldb type unit support to the release notes

Reviewers: JDevlieghere, teemperor

Subscribers: llvm-commits, lldb-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365568 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoGlobalISel: Combine unmerge of merge with intermediate cast
Matt Arsenault [Tue, 9 Jul 2019 22:19:13 +0000 (22:19 +0000)]
GlobalISel: Combine unmerge of merge with intermediate cast

This eliminates some illegal intermediate vectors when operations are
scalarized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365566 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Profile] Support raw/indexed profiles larger than 4GB
Vedant Kumar [Tue, 9 Jul 2019 22:01:04 +0000 (22:01 +0000)]
[Profile] Support raw/indexed profiles larger than 4GB

rdar://45955976

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365565 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[llvm-objdump] Keep warning for --disassemble-functions in correct order.
Yuanfang Chen [Tue, 9 Jul 2019 21:53:33 +0000 (21:53 +0000)]
[llvm-objdump] Keep warning for --disassemble-functions in correct order.

relative to normal output when dumping archive files.

prepare for PR35351.

Reviewers: jhenderson, grimar, MaskRay, rupprecht

Reviewed by: MaskRay, jhenderson

Differential Revision: https://reviews.llvm.org/D64165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365564 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AMDGPU] gfx908 mAI instructions, MC part
Stanislav Mekhanoshin [Tue, 9 Jul 2019 21:43:09 +0000 (21:43 +0000)]
[AMDGPU] gfx908 mAI instructions, MC part

Differential Revision: https://reviews.llvm.org/D64446

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365563 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[SLP] Optimize getSpillCost(); NFCI
Nikita Popov [Tue, 9 Jul 2019 20:24:44 +0000 (20:24 +0000)]
[SLP] Optimize getSpillCost(); NFCI

For a given set of live values, the spill cost will always be the
same for each call. Compute the cost once and multiply it by the
number of calls.

(I'm not sure this spill cost modeling makes sense if there are
multiple calls, as the spill cost will likely be shared across
calls in that case. But that's how it currently works.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365552 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agohwasan: Improve precision of checks using short granule tags.
Peter Collingbourne [Tue, 9 Jul 2019 20:22:36 +0000 (20:22 +0000)]
hwasan: Improve precision of checks using short granule tags.

A short granule is a granule of size between 1 and `TG-1` bytes. The size
of a short granule is stored at the location in shadow memory where the
granule's tag is normally stored, while the granule's actual tag is stored
in the last byte of the granule. This means that in order to verify that a
pointer tag matches a memory tag, HWASAN must check for two possibilities:

* the pointer tag is equal to the memory tag in shadow memory, or
* the shadow memory tag is actually a short granule size, the value being loaded
  is in bounds of the granule and the pointer tag is equal to the last byte of
  the granule.

Pointer tags between 1 to `TG-1` are possible and are as likely as any other
tag. This means that these tags in memory have two interpretations: the full
tag interpretation (where the pointer tag is between 1 and `TG-1` and the
last byte of the granule is ordinary data) and the short tag interpretation
(where the pointer tag is stored in the granule).

When HWASAN detects an error near a memory tag between 1 and `TG-1`, it
will show both the memory tag and the last byte of the granule. Currently,
it is up to the user to disambiguate the two possibilities.

Because this functionality obsoletes the right aligned heap feature of
the HWASAN memory allocator (and because we can no longer easily test
it), the feature is removed.

Also update the documentation to cover both short granule tags and
outlined checks.

Differential Revision: https://reviews.llvm.org/D63908

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365551 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[PoisonChecking] Flesh out complete todo list for full coverage
Philip Reames [Tue, 9 Jul 2019 19:59:39 +0000 (19:59 +0000)]
[PoisonChecking] Flesh out complete todo list for full coverage

Note: I don't actually plan to implement all of the cases at the moment, I'm just documenting them for completeness.  There's a couple of cases left which are practically useful for me in debugging loop transforms, and I'll probably stop there for the moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365550 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBenefici...
Craig Topper [Tue, 9 Jul 2019 19:55:28 +0000 (19:55 +0000)]
[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it

Basically the problem is that X86 doesn't set the Fast flag from
allowsMemoryAccess on certain CPUs due to slow unaligned memory
subtarget features. This prevents bitcasts from being folded into
loads and stores. But all vector loads and stores of the same width
are the same cost on X86.

This patch merges the allowsMemoryAccess call into isLoadBitCastBeneficial to allow X86 to skip it.

Differential Revision: https://reviews.llvm.org/D64295

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365549 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix build error for VC STL, use llvm::make_unique
Reid Kleckner [Tue, 9 Jul 2019 19:51:58 +0000 (19:51 +0000)]
Fix build error for VC STL, use llvm::make_unique

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365548 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AMDGPU] gfx908 register file changes
Stanislav Mekhanoshin [Tue, 9 Jul 2019 19:41:51 +0000 (19:41 +0000)]
[AMDGPU] gfx908 register file changes

Differential Revision: https://reviews.llvm.org/D64438

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365546 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[PoisonCheker] Support for out of bounds operands on shifts + insert/extractelement
Philip Reames [Tue, 9 Jul 2019 19:26:12 +0000 (19:26 +0000)]
[PoisonCheker] Support for out of bounds operands on shifts + insert/extractelement

These are sources of poison which don't come from flags, but are clearly documented in the LangRef.  Left off support for scalable vectors for the moment, but should be easy to add if anyone is interested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365543 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoBoilerplate for producing XCOFF object files from the PowerPC backend.
Sean Fertile [Tue, 9 Jul 2019 19:21:01 +0000 (19:21 +0000)]
Boilerplate for producing XCOFF object files from the PowerPC backend.

Stubs out a number of the classes needed to produce a new object file format
(XCOFF) for the powerpc-aix target. For testing input is an empty module which
produces an object file with just a file header.

Differential Revision: https://reviews.llvm.org/D61694

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365541 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[X86] LowerToHorizontalOp - use count_if to count non-UNDEF ops. NFCI.
Simon Pilgrim [Tue, 9 Jul 2019 19:19:17 +0000 (19:19 +0000)]
[X86] LowerToHorizontalOp - use count_if to count non-UNDEF ops. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365540 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[PoisonChecking] Add validation rules for "exact" on sdiv/udiv
Philip Reames [Tue, 9 Jul 2019 18:56:41 +0000 (18:56 +0000)]
[PoisonChecking] Add validation rules for "exact" on sdiv/udiv

As directly stated in the LangRef, no ambiguity here...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365538 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ThinLTO] only emit used or referenced CFI records to index
Bob Haarman [Tue, 9 Jul 2019 18:50:55 +0000 (18:50 +0000)]
[ThinLTO] only emit used or referenced CFI records to index

Summary: We emit CFI_FUNCTION_DEFS and CFI_FUNCTION_DECLS to
distributed ThinLTO indices to implement indirect function call
checking.  This change causes us to only emit entries for functions
that are either defined or used by the module we're writing the index
for (instead of all functions in the combined index), which can make
the indices substantially smaller.

Fixes PR42378.

Reviewers: pcc, vitalybuka, eugenis

Subscribers: mehdi_amini, hiraditya, dexonsmith, arphaman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63887

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365537 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAdd a transform pass to make the executable semantics of poison explicit in the IR
Philip Reames [Tue, 9 Jul 2019 18:49:29 +0000 (18:49 +0000)]
Add a transform pass to make the executable semantics of poison explicit in the IR

Implements a transform pass which instruments IR such that poison semantics are made explicit. That is, it provides a (possibly partial) executable semantics for every instruction w.r.t. poison as specified in the LLVM LangRef. There are obvious parallels to the sanitizer tools, but this pass is focused purely on the semantics of LLVM IR, not any particular source language.

The target audience for this tool is developers working on or targetting LLVM from a frontend. The idea is to be able to take arbitrary IR (with the assumption of known inputs), and evaluate it concretely after having made poison semantics explicit to detect cases where either a) the original code executes UB, or b) a transform pass introduces UB which didn't exist in the original program.

At the moment, this is mostly the framework and still needs to be fleshed out. By reusing existing code we have decent coverage, but there's a lot of cases not yet handled. What's here is good enough to handle interesting cases though; for instance, one of the recent LFTR bugs involved UB being triggered by integer induction variables with nsw/nuw flags would be reported by the current code.

(See comment in PoisonChecking.cpp for full explanation and context)

Differential Revision: https://reviews.llvm.org/D64215

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365536 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoTry to appease the Windows build bots.
Sean Fertile [Tue, 9 Jul 2019 18:44:28 +0000 (18:44 +0000)]
Try to appease the Windows build bots.

Several of the conditonal operators commited in llvm-svn: 365524 fail to compile
on the windows buildbots. Converting to an if and early return to try to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365535 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[BPF] Fix a typo in the file name
Yonghong Song [Tue, 9 Jul 2019 18:35:46 +0000 (18:35 +0000)]
[BPF] Fix a typo in the file name

Fixed the file name from BPFAbstrctMemberAccess.cpp to
BPFAbstractMemberAccess.cpp.

Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365532 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agogn build: Merge r365503.
Peter Collingbourne [Tue, 9 Jul 2019 18:30:38 +0000 (18:30 +0000)]
gn build: Merge r365503.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365530 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[unittest] Add the missing bogus machine register info initialization.
Michael Liao [Tue, 9 Jul 2019 18:22:48 +0000 (18:22 +0000)]
[unittest] Add the missing bogus machine register info initialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365529 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AMDGPU] gfx908 target
Stanislav Mekhanoshin [Tue, 9 Jul 2019 18:10:06 +0000 (18:10 +0000)]
[AMDGPU] gfx908 target

Differential Revision: https://reviews.llvm.org/D64429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365525 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[Object][XCOFF] Add support for 64-bit file header and section header dumping.
Sean Fertile [Tue, 9 Jul 2019 18:09:11 +0000 (18:09 +0000)]
[Object][XCOFF] Add support for 64-bit file header and section header dumping.

Adds a readobj dumper for 32-bit and 64-bit section header tables, and extend
support for the file-header dumping to include 64-bit object files. Also
refactors the binary file parsing to be done in a helper function in an attempt
to cleanup error handeling.

Differential Revision: https://reviews.llvm.org/D63843

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365524 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[InstCombine] add tests for trunc(load); NFC
Sanjay Patel [Tue, 9 Jul 2019 18:06:16 +0000 (18:06 +0000)]
[InstCombine] add tests for trunc(load); NFC

I'm not sure if transforming any of these is valid as
a target-independent fold, but we might as well have
a few tests here to confirm or deny our position.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365523 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAMDGPU: Fix test failing since r365512
Matt Arsenault [Tue, 9 Jul 2019 17:54:34 +0000 (17:54 +0000)]
AMDGPU: Fix test failing since r365512

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365521 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoRevert "[HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfi...
Jinsong Ji [Tue, 9 Jul 2019 17:53:09 +0000 (17:53 +0000)]
Revert "[HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfitable()"

This reverts commit d95557306585404893d610784edb3e32f1bfce18.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365520 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAdd lit.local.cfg to llvm-objdump tests
Steven Wu [Tue, 9 Jul 2019 17:47:14 +0000 (17:47 +0000)]
Add lit.local.cfg to llvm-objdump tests

Add configuration file to llvm-objdump tests to treat files with .yaml
extension as tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365519 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoRemove a comment that has been obsolete since r327679
Nico Weber [Tue, 9 Jul 2019 17:19:47 +0000 (17:19 +0000)]
Remove a comment that has been obsolete since r327679

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365517 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[unittest] Add bogus register info.
Michael Liao [Tue, 9 Jul 2019 17:19:01 +0000 (17:19 +0000)]
[unittest] Add bogus register info.

Reviewers: dstenb

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64421

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365516 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoRename llvm/test/tools/llvm-pdbdump to llvm/test/tools/llvm-pdbutil
Nico Weber [Tue, 9 Jul 2019 17:14:24 +0000 (17:14 +0000)]
Rename llvm/test/tools/llvm-pdbdump to llvm/test/tools/llvm-pdbutil

llvm-pdbdump was renamed to llvm-pdbutil long ago. This updates the test
to be where you'd expect them to be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365515 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMake pdbdump-objfilename test work again
Nico Weber [Tue, 9 Jul 2019 17:02:51 +0000 (17:02 +0000)]
Make pdbdump-objfilename test work again

- The test had extension .yaml, which lit doesn't execute in this
  directory. Rename to .test to make it run, and move the yaml bits
  into a dedicated file, like with all other tests in this dir.

- llvm-pdbdump got renamed to llvm-pdbutil long ago, update test.

- -dbi-module-info got renamed in r305032, update test for this too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365514 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AMDGPU] Created a sub-register class for the return address operand in the return...
Christudasan Devadasan [Tue, 9 Jul 2019 16:48:42 +0000 (16:48 +0000)]
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.

Function return instruction lowering, currently uses the fixed register pair s[30:31] for holding
the return address. It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class
exclusive of the CSRs, and used this regclass while lowering the return instruction.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D63924

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365512 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[RISCV] Fix ICE in isDesirableToCommuteWithShift
Sam Elliott [Tue, 9 Jul 2019 16:24:16 +0000 (16:24 +0000)]
[RISCV] Fix ICE in isDesirableToCommuteWithShift

Summary:
There was an error being thrown from isDesirableToCommuteWithShift in
some tests. This was tracked down to the method being called before
legalisation, with an extended value type, not a machine value type.

In the case I diagnosed, the error was only hit with an instruction sequence
involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is
instead an Extended ValueType which was causing the issue.

I have added a test to cover this case, and fixed the error in the callback.

Reviewers: asb, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64425

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365511 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches
Amara Emerson [Tue, 9 Jul 2019 16:05:59 +0000 (16:05 +0000)]
[AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches

If we have an icmp->brcond->br sequence where the brcond just branches to the
next block jumping over the br, while the br takes the false edge, then we can
modify the conditional branch to jump to the br's target while inverting the
condition of the incoming icmp. This means we can eliminate the br as an
unconditional branch to the fallthrough block.

Differential Revision: https://reviews.llvm.org/D64354

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365510 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[mips] Show error in case of using FP64 mode on pre MIPS32R2 CPU
Simon Atanasyan [Tue, 9 Jul 2019 15:48:16 +0000 (15:48 +0000)]
[mips] Show error in case of using FP64 mode on pre MIPS32R2 CPU

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365508 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC
Simon Atanasyan [Tue, 9 Jul 2019 15:48:05 +0000 (15:48 +0000)]
[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC

Support for 64-bit coprocessors on a 32-bit architecture
was added in `MIPS32 R2`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365507 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC] Fixed tests
David Bolvansky [Tue, 9 Jul 2019 15:31:36 +0000 (15:31 +0000)]
[NFC] Fixed tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365506 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[DAGCombine] LoadedSlice - keep getOffsetFromBase() uint64_t offset. NFCI.
Simon Pilgrim [Tue, 9 Jul 2019 15:28:57 +0000 (15:28 +0000)]
[DAGCombine] LoadedSlice - keep getOffsetFromBase() uint64_t offset. NFCI.

Keep the uint64_t type from getOffsetFromBase() to stop truncation/extension overflow warnings in MSVC in alignment math.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365504 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[BPF] Support for compile once and run everywhere
Yonghong Song [Tue, 9 Jul 2019 15:28:41 +0000 (15:28 +0000)]
[BPF] Support for compile once and run everywhere

Introduction
============

This patch added intial support for bpf program compile once
and run everywhere (CO-RE).

The main motivation is for bpf program which depends on
kernel headers which may vary between different kernel versions.
The initial discussion can be found at https://lwn.net/Articles/773198/.

Currently, bpf program accesses kernel internal data structure
through bpf_probe_read() helper. The idea is to capture the
kernel data structure to be accessed through bpf_probe_read()
and relocate them on different kernel versions.

On each host, right before bpf program load, the bpfloader
will look at the types of the native linux through vmlinux BTF,
calculates proper access offset and patch the instruction.

To accommodate this, three intrinsic functions
   preserve_{array,union,struct}_access_index
are introduced which in clang will preserve the base pointer,
struct/union/array access_index and struct/union debuginfo type
information. Later, bpf IR pass can reconstruct the whole gep
access chains without looking at gep itself.

This patch did the following:
  . An IR pass is added to convert preserve_*_access_index to
    global variable who name encodes the getelementptr
    access pattern. The global variable has metadata
    attached to describe the corresponding struct/union
    debuginfo type.
  . An SimplifyPatchable MachineInstruction pass is added
    to remove unnecessary loads.
  . The BTF output pass is enhanced to generate relocation
    records located in .BTF.ext section.

Typical CO-RE also needs support of global variables which can
be assigned to different values to different hosts. For example,
kernel version can be used to guard different versions of codes.
This patch added the support for patchable externals as well.

Example
=======

The following is an example.

  struct pt_regs {
    long arg1;
    long arg2;
  };
  struct sk_buff {
    int i;
    struct net_device *dev;
  };

  #define _(x) (__builtin_preserve_access_index(x))
  static int (*bpf_probe_read)(void *dst, int size, const void *unsafe_ptr) =
          (void *) 4;
  extern __attribute__((section(".BPF.patchable_externs"))) unsigned __kernel_version;
  int bpf_prog(struct pt_regs *ctx) {
    struct net_device *dev = 0;

    // ctx->arg* does not need bpf_probe_read
    if (__kernel_version >= 41608)
      bpf_probe_read(&dev, sizeof(dev), _(&((struct sk_buff *)ctx->arg1)->dev));
    else
      bpf_probe_read(&dev, sizeof(dev), _(&((struct sk_buff *)ctx->arg2)->dev));
    return dev != 0;
  }

In the above, we want to translate the third argument of
bpf_probe_read() as relocations.

  -bash-4.4$ clang -target bpf -O2 -g -S trace.c

The compiler will generate two new subsections in .BTF.ext,
OffsetReloc and ExternReloc.
OffsetReloc is to record the structure member offset operations,
and ExternalReloc is to record the external globals where
only u8, u16, u32 and u64 are supported.

   BPFOffsetReloc Size
   struct SecLOffsetReloc for ELF section #1
   A number of struct BPFOffsetReloc for ELF section #1
   struct SecOffsetReloc for ELF section #2
   A number of struct BPFOffsetReloc for ELF section #2
   ...
   BPFExternReloc Size
   struct SecExternReloc for ELF section #1
   A number of struct BPFExternReloc for ELF section #1
   struct SecExternReloc for ELF section #2
   A number of struct BPFExternReloc for ELF section #2

  struct BPFOffsetReloc {
    uint32_t InsnOffset;    ///< Byte offset in this section
    uint32_t TypeID;        ///< TypeID for the relocation
    uint32_t OffsetNameOff; ///< The string to traverse types
  };

  struct BPFExternReloc {
    uint32_t InsnOffset;    ///< Byte offset in this section
    uint32_t ExternNameOff; ///< The string for external variable
  };

Note that only externs with attribute section ".BPF.patchable_externs"
are considered for Extern Reloc which will be patched by bpf loader
right before the load.

For the above test case, two offset records and one extern record
will be generated:
  OffsetReloc records:
        .long   .Ltmp12                 # Insn Offset
        .long   7                       # TypeId
        .long   242                     # Type Decode String
        .long   .Ltmp18                 # Insn Offset
        .long   7                       # TypeId
        .long   242                     # Type Decode String

  ExternReloc record:
        .long   .Ltmp5                  # Insn Offset
        .long   165                     # External Variable

  In string table:
        .ascii  "0:1"                   # string offset=242
        .ascii  "__kernel_version"      # string offset=165

The default member offset can be calculated as
    the 2nd member offset (0 representing the 1st member) of struct "sk_buff".

The asm code:
    .Ltmp5:
    .Ltmp6:
            r2 = 0
            r3 = 41608
    .Ltmp7:
    .Ltmp8:
            .loc    1 18 9 is_stmt 0        # t.c:18:9
    .Ltmp9:
            if r3 > r2 goto LBB0_2
    .Ltmp10:
    .Ltmp11:
            .loc    1 0 9                   # t.c:0:9
    .Ltmp12:
            r2 = 8
    .Ltmp13:
            .loc    1 19 66 is_stmt 1       # t.c:19:66
    .Ltmp14:
    .Ltmp15:
            r3 = *(u64 *)(r1 + 0)
            goto LBB0_3
    .Ltmp16:
    .Ltmp17:
    LBB0_2:
            .loc    1 0 66 is_stmt 0        # t.c:0:66
    .Ltmp18:
            r2 = 8
            .loc    1 21 66 is_stmt 1       # t.c:21:66
    .Ltmp19:
            r3 = *(u64 *)(r1 + 8)
    .Ltmp20:
    .Ltmp21:
    LBB0_3:
            .loc    1 0 66 is_stmt 0        # t.c:0:66
            r3 += r2
            r1 = r10
    .Ltmp22:
    .Ltmp23:
    .Ltmp24:
            r1 += -8
            r2 = 8
            call 4

For instruction .Ltmp12 and .Ltmp18, "r2 = 8", the number
8 is the structure offset based on the current BTF.
Loader needs to adjust it if it changes on the host.

For instruction .Ltmp5, "r2 = 0", the external variable
got a default value 0, loader needs to supply an appropriate
value for the particular host.

Compiling to generate object code and disassemble:
   0000000000000000 bpf_prog:
           0:       b7 02 00 00 00 00 00 00         r2 = 0
           1:       7b 2a f8 ff 00 00 00 00         *(u64 *)(r10 - 8) = r2
           2:       b7 02 00 00 00 00 00 00         r2 = 0
           3:       b7 03 00 00 88 a2 00 00         r3 = 41608
           4:       2d 23 03 00 00 00 00 00         if r3 > r2 goto +3 <LBB0_2>
           5:       b7 02 00 00 08 00 00 00         r2 = 8
           6:       79 13 00 00 00 00 00 00         r3 = *(u64 *)(r1 + 0)
           7:       05 00 02 00 00 00 00 00         goto +2 <LBB0_3>

    0000000000000040 LBB0_2:
           8:       b7 02 00 00 08 00 00 00         r2 = 8
           9:       79 13 08 00 00 00 00 00         r3 = *(u64 *)(r1 + 8)

    0000000000000050 LBB0_3:
          10:       0f 23 00 00 00 00 00 00         r3 += r2
          11:       bf a1 00 00 00 00 00 00         r1 = r10
          12:       07 01 00 00 f8 ff ff ff         r1 += -8
          13:       b7 02 00 00 08 00 00 00         r2 = 8
          14:       85 00 00 00 04 00 00 00         call 4

Instructions #2, #5 and #8 need relocation resoutions from the loader.

Signed-off-by: Yonghong Song <yhs@fb.com>
Differential Revision: https://reviews.llvm.org/D61524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365503 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[ADT] Remove MSVC-only "no two-phase name lookup" typename path.
Simon Pilgrim [Tue, 9 Jul 2019 15:24:19 +0000 (15:24 +0000)]
[ADT] Remove MSVC-only "no two-phase name lookup" typename path.

Now that we've dropped VS2015 support (D64326) we can use the regular codepath as VS2017+ correctly handles it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365502 91177308-0d34-0410-b5e6-96231b3b80d8

5 years ago[NFC] Added tests for D64285
David Bolvansky [Tue, 9 Jul 2019 15:12:01 +0000 (15:12 +0000)]
[NFC] Added tests for D64285

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365501 91177308-0d34-0410-b5e6-96231b3b80d8