David Blaikie [Mon, 16 Jan 2017 20:36:26 +0000 (20:36 +0000)]
[XRay] Implement the `llvm-xray graph` subcommand
Here we define the `graph` subcommand which generates a graph from the function
call information and uses it to present the call information graphically with
additional annotations.
Tony Jiang [Mon, 16 Jan 2017 20:12:26 +0000 (20:12 +0000)]
[PowerPC] Expand ISEL instruction into if-then-else sequence.
Generally, the ISEL is expanded into if-then-else sequence, in some
cases (like when the destination register is the same with the true
or false value register), it may just be expanded into just the if
or else sequence.
Sanjay Patel [Mon, 16 Jan 2017 20:05:26 +0000 (20:05 +0000)]
[InstCombine] fix names in canEvaluateShiftedShift(); NFC
It's not clear what 'First' and 'Second' mean, so use 'Inner' and 'Outer'
to match foldShiftedShift() and add comments with formulas, so it's easier
to see what's going on.
Falkor only partially implements the ARMv8.1a extensions, so this patch
refactors the support for the SQRDML[A|S]H instruction into a separate
feature.
Hal Finkel [Mon, 16 Jan 2017 15:22:01 +0000 (15:22 +0000)]
Fix use-after-free bug in AffectedValueCallbackVH::allUsesReplacedWith
When transferring affected values in the cache from an old value, identified by
the value of the current callback, to the specified new value we might need to
insert a new entry into the DenseMap which constitutes the cache. Doing so
might delete the current callback object. Move the copying logic into a new
function, a member of the assumption cache itself, so that we don't run into UB
should the callback handle itself be removed mid-copy.
Daniel Sanders [Mon, 16 Jan 2017 15:20:43 +0000 (15:20 +0000)]
[globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Tony Jiang [Mon, 16 Jan 2017 14:43:12 +0000 (14:43 +0000)]
[PowerPC] Expand ISEL instruction into if-then-else sequence.
Generally, the ISEL is expanded into if-then-else sequence, in some
cases (like when the destination register is the same with the true
or false value register), it may just be expanded into just the if
or else sequence.
Craig Topper [Mon, 16 Jan 2017 00:55:58 +0000 (00:55 +0000)]
[AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQD
with ZMM index. Similar for SCATTER and the prefetch gather and scatter
instructions.
Justin Lebar [Sun, 15 Jan 2017 16:54:35 +0000 (16:54 +0000)]
[NVPTX] Let there be One True Way to set NVVMReflect params.
Summary:
Previously there were three ways to inform the NVVMReflect pass whether
you wanted to flush denormals to zero:
* An LLVM command-line option
* Parameters to the NVVMReflect constructor
* Metadata on the module itself.
This change removes the first two, leaving only the third.
The motivation for this change, aside from simplifying things, is that
we want LLVM to be aware of whether it's operating in FTZ mode, so other
passes can use this information. Ideally we'd have a target-generic
piece of metadata on the module. This change moves us in that
direction.
Daniel Jasper [Sun, 15 Jan 2017 16:42:36 +0000 (16:42 +0000)]
Fix un-initialized error introduced by r291959.
This is uncovered when running tools/dsymutil/X86/empty_range.s.test
with ASAN. Haven't investigate yet, whether that means there is an ODR
violation in that test.
Chandler Carruth [Sun, 15 Jan 2017 09:29:27 +0000 (09:29 +0000)]
[PM] Clean up the testing for IVUsers, especially with the new PM.
First, I've moved a test of IVUsers from the LSR tree to a dedicated
IVUsers test directory. I've also simplified its RUN line now that the
new pass manager's loop PM is providing analyses on their own.
No functionality changed, but it makes subsequent changes cleaner.
Chandler Carruth [Sun, 15 Jan 2017 08:20:50 +0000 (08:20 +0000)]
[PM] Teach the optimization remarks emitter to handle invalidation
events.
This pass sometimes has a pointer to BlockFrequencyInfo so it needs
custom invalidation logic. It is also otherwise immutable so we can
reduce the number of invalidations that happen substantially.
Lang Hames [Sun, 15 Jan 2017 06:34:25 +0000 (06:34 +0000)]
[Orc][RPC] Add an RPCFunctionNotSupported error type and return it from
negotiateFunction where appropriate.
Replacing the old ECError with a custom type allows us to attach the name of
the function that could not be negotiated, enabling better diagnostics for
negotiation failures.
Chandler Carruth [Sun, 15 Jan 2017 06:32:49 +0000 (06:32 +0000)]
[PM] Introduce an analysis set used to preserve all analyses over
a function's CFG when that CFG is unchanged.
This allows transformation passes to simply claim they preserve the CFG
and analysis passes to check for the CFG being preserved to remove the
fanout of all analyses being listed in all passes.
I've gone through and removed or cleaned up as many of the comments
reminding us to do this as I could.
Craig Topper [Sun, 15 Jan 2017 05:21:29 +0000 (05:21 +0000)]
[X86] Remove untested MOVDDUP patterns.
These all involve bitcasts around the memory operands. This isn't
something we normally do for isel patterns. I suspect DAG combine should
convert the load type making this unnecessary.
Mehdi Amini [Sun, 15 Jan 2017 03:21:30 +0000 (03:21 +0000)]
Add a LLVM_USE_LINKER that defines the linker to use when building LLVM
Summary:
This string parameter is passed to -fuse-ld when linking. It can be
an absolute path to your custom linker, otherwise clang will look for
`ld.{name}`.
Rui Ueyama [Sun, 15 Jan 2017 00:36:02 +0000 (00:36 +0000)]
PDB: Add a class to create the /names stream contents.
This patch adds a new class NameHashTableBuilder which creates /names streams.
This patch contains a test to confirm that a stream created by
NameHashTableBuilder can be read by NameHashTable reader class.
Chandler Carruth [Sun, 15 Jan 2017 00:26:18 +0000 (00:26 +0000)]
[PM] The assumption cache is fundamentally designed to be self-updating,
mark it as never invalidated in the new PM.
The old PM already required this to work, and after a discussion with
Hal this seems to really be the only sensible answer. The cache
gracefully degrades as the IR is mutated, and most things which do this
should already be incrementally updating the cache.
This gets rid of a bunch of logic preserving and testing the
invalidation of this analysis.
Chandler Carruth [Sat, 14 Jan 2017 23:25:22 +0000 (23:25 +0000)]
[PM] Fix instcombine's analysis preservation in the new pass manager to
cover domtree and alias analysis. These are the pretty clear analyses
that we would always want to survive this pass.
To make these survive, we also need to preserve the assumption cache.
Added a test that verifies the important bits of this preservation.
David Majnemer [Sat, 14 Jan 2017 21:54:58 +0000 (21:54 +0000)]
Adding const overloads of operator* and operator-> for DenseSet iterators
This fixes some problems when building ClangDiagnostics.cpp on Visual Studio 2017 RC. As far as I understand, there was a change in the implementation of the constructor for std::vector with two iterator parameters, which in our case causes an attempt to dereference const Iterator objects. Since there was no overload for a const Iterator, the compile would fail.
Simon Pilgrim [Sat, 14 Jan 2017 13:07:22 +0000 (13:07 +0000)]
[X86][XOP] Add tests for integer fused multiply add
Tests showing missed opportunities to use XOP's integer fma instructions
Some of these are pretty awkward to match as they often have implicit sext/trunc stages but many just ignore overflow bits which makes things pretty straightforward.
Craig Topper [Sat, 14 Jan 2017 07:50:52 +0000 (07:50 +0000)]
[AVX-512] Teach two address instruction pass to replace masked move instructions with blendm instructions when its beneficial.
Isel now selects masked move instructions for vselect instead of blendm. But sometimes it beneficial to register allocation to remove the tied register constraint by using blendm instructions.
This also picks up cases where the masked move was created due to a masked load intrinsic.
Craig Topper [Sat, 14 Jan 2017 07:29:24 +0000 (07:29 +0000)]
[AVX-512] Replace V_SET0 in AVX-512 patterns with AVX512_128_SET0. Enhance AVX512_128_SET0 expansion to make this possible.
We'll now expand AVX512_128_SET0 to an EVEX VXORD if VLX available. Or if its not, but register allocation has selected a non-extended register we will use VEX VXORPS. And if its an extended register without VLX we'll use a 512-bit XOR. Do the same for AVX512_FsFLD0SS/SD.
This makes it possible for the register allocator to have all 32 registers available to work with.
This fallthrough if other cases are added between fabs and default
could cause fabs to fall to the next case resulting in a bug.
Better getting rid of it immediately just to be sure.
projects / llvm / log