Diego Novillo [Wed, 18 Jun 2014 18:46:58 +0000 (18:46 +0000)]
Simply test for available locations in optimization remarks.
When emitting optimization remarks, we test for the presence of
instruction locations by testing for a valid llvm.dbg.cu annotation.
This is slightly inefficient because we can simply ask whether the
debug location we have is known or not.
Additionally, if my current plan works, I will need to remove the
llvm.dbg.cu annotation from the IL (or prevent it from being generated)
when -Rpass is used without -g. In those cases, we'll want to generate
line tables but we will want to prevent code generation from emitting
DWARF code for them.
Ulrich Weigand [Wed, 18 Jun 2014 18:33:36 +0000 (18:33 +0000)]
[PowerPC] Remove unnecessary load of r12 in indirect call
When looking at the 64-bit SVR4 indirect call sequence, I noticed
an unnecessary load of r12. And indeed the code says:
// R12 must contain the address of an indirect callee.
But this is not correct; in the 64-bit SVR4 (ELFv1) ABI, there is
no need to load r12 at this point. It seems this code and comment
is a remnant of code originally shared with the Darwin ABI ...
let RST = 2, DS = 10, RA = 1 in
def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
"ld 2, 40(1)", IIC_LdStLD,
[(PPCtoc_restore)]>, isPPC64;
Note that these not only restrict the destination of the
load to r2, but they also restrict the *source* of the
load to particular address combinations. The latter is
a problem when we want to support the ELFv2 ABI, since
there the TOC save slot is no longer at 40(1).
This patch replaces those two instructions with a single
instruction pattern that only hard-codes r2 as destination,
but supports generic addresses as source. This will allow
supporting the ELFv2 ABI, and also helps generate more
efficient code for calls to absolute addresses (allowing
simplification of the ppc64-calls.ll test case).
Ulrich Weigand [Wed, 18 Jun 2014 17:28:56 +0000 (17:28 +0000)]
[PowerPC] Add back test case for absolute calls (removed in r211174)
As requested by Hal Finkel, this adds back a test for calls to
a known-constant function pointer value, and verifies that the
64-bit SVR4 indirect function call sequence is used.
Adam Nemet [Wed, 18 Jun 2014 16:51:10 +0000 (16:51 +0000)]
[X86] AVX512: Add non-temporal stores
Note that I followed the AVX2 convention here and didn't add LLVM intrinsics
for stores. These can be generated with the nontemporal hint on LLVM IR
stores (see new test). The GCC builtins are lowered directly into nontemporal
stores.
Ulrich Weigand [Wed, 18 Jun 2014 16:14:04 +0000 (16:14 +0000)]
[PowerPC] Do not use BLA with the 64-bit SVR4 ABI
The PowerPC back-end uses BLA to implement calls to functions at
known-constant addresses, which is apparently used for certain
system routines on Darwin.
However, with the 64-bit SVR4 ABI, this is actually incorrect.
An immediate function pointer value on this platform is not
directly usable as a target address for BLA:
- in the ELFv1 ABI, the function pointer value refers to the
*function descriptor*, not the code address
- in the ELFv2 ABI, the function pointer value refers to the
global entry point, but BL(A) would only be correct when
calling the *local* entry point
This bug didn't show up since using immediate function pointer
values is not usually done in the 64-bit SVR4 ABI in the first
place. However, I ran into this issue with a certain use case
of LLVM as JIT, where immediate function pointer values were
uses to implement callbacks from JITted code to helpers in
statically compiled code.
Fixed by simply not using BLA with the 64-bit SVR4 ABI.
Ulrich Weigand [Wed, 18 Jun 2014 15:52:18 +0000 (15:52 +0000)]
Do not XFAIL test/tools/llvm-cov tests on powerpc64le
All tests in test/tools/llvm-cov fail on big-endian targets and are
supposed to be XFAILed there. However, including "powerpc64" in the
XFAIL line is now incorrect, since that matches both powerpc64- and
powerpc64le- targets, and the tests pass on the latter.
Update the XFAIL lines to use powerpc64- instead (like mips64-).
Ulrich Weigand [Wed, 18 Jun 2014 15:37:07 +0000 (15:37 +0000)]
[PowerPC] Fix emitting instruction pairs on LE
My patch r204634 to emit instructions in little-endian format failed to
handle those special cases where we emit a pair of instructions from a
single LLVM MC instructions (like the bl; nop pairs used to implement
the call sequence).
In those cases, we still need to emit the "first" instruction (the one
in the more significant word) first, on both big and little endian,
and not swap them.
Ulrich Weigand [Wed, 18 Jun 2014 15:15:49 +0000 (15:15 +0000)]
Support LE in RelocVisitor::visitELF_PPC64_*
Since we now support both LE and BE PPC64 variants, use of getAddend64BE
is no longer correct. Use the generic getELFRelocationAddend instead,
as was already done for Mips.
Matheus Almeida [Wed, 18 Jun 2014 14:49:56 +0000 (14:49 +0000)]
[mips] Fix expansion of memory operation if destination register is not a GPR.
Summary:
The assembler tries to reuse the destination register for memory operations whenever
it can but it's not possible to do so if the destination register is not a GPR.
Example:
ldc1 $f0, sym
should expand to:
lui $at, %hi(sym)
ldc1 $f0, %lo(sym)($at)
It's entirely wrong to expand to:
lui $f0, %hi(sym)
ldc1 $f0, %lo(sym)($f0)
Matheus Almeida [Wed, 18 Jun 2014 14:15:42 +0000 (14:15 +0000)]
[mips] Access $at only if necessary.
Summary:
This patch doesn't really change the logic behind expandMemInst but it allows
us to assemble .S files that use .set noat with some macros. For example:
.set noat
lw $k0, offset($k1)
Can expand to:
lui $k0, %hi(offset)
addu $k0, $k0, $k1
lw $k0, %lo(offset)($k0)
Tim Northover [Wed, 18 Jun 2014 11:52:44 +0000 (11:52 +0000)]
DAG: move sret demotion into most basic LowerCallTo implementation.
It looks like there are two versions of LowerCallTo here: the
SelectionDAGBuilder one is designed to operate on LLVM IR, and the
TargetLowering one in the case where everything is at DAG level.
Previously, only the SelectionDAGBuilder variant could handle demoting
an impossible return to sret semantics (before delegating to the
TargetLowering version), but this functionality is also useful for
certain libcalls (e.g. 128-bit operations on 32-bit x86). So this
commit moves the sret handling down a level.
JF Bastien [Wed, 18 Jun 2014 06:23:25 +0000 (06:23 +0000)]
Random Number Generator (llvm)
Summary:
Provides an abstraction for a random number generator (RNG) that produces a stream of pseudo-random numbers.
The current implementation uses C++11 facilities and is therefore not cryptographically secure.
The RNG is salted with the text of the current command line invocation.
In addition, a user may specify a seed (reproducible builds).
In clang, the seed can be set via
-frandom-seed=X
In the back end, the seed can be set via
-rng-seed=X
This is the llvm part of the patch.
clang part: D3391
Kevin Qin [Wed, 18 Jun 2014 05:54:42 +0000 (05:54 +0000)]
[AArch64] Fix a pattern match failure caused by creating improper CONCAT_VECTOR.
ReconstructShuffle() may wrongly creat a CONCAT_VECTOR trying to
concat 2 of v2i32 into v4i16. This commit is to fix this issue and
try to generate UZP1 instead of lots of MOV and INS.
Patch is initalized by Kevin Qin, and refactored by Tim Northover.
Louis Gerbarg [Tue, 17 Jun 2014 23:22:41 +0000 (23:22 +0000)]
Allow X86FastIsel to cope with 64 bit absolute relocations
This patch is a follow up to r211040 & r211052. Rather than bailing out of fast
isel this patch will generate an alternate instruction (movabsq) instead of the
leaq. While this will always have enough room to handle the 64 bit displacment
it is generally over kill for internal symbols (most displacements will be
within 32 bits) but since we have no way of communicating the code model to the
the assmebler in order to avoid flagging an absolute leal/leaq as illegal when
using a symbolic displacement.
Zachary Turner [Tue, 17 Jun 2014 21:54:18 +0000 (21:54 +0000)]
Remove more occurrences of the unused-mutex-parameter pattern.
This pattern loses some of its usefulness when the mutex type is
statically polymorphic as opposed to runtime polymorphic, as
swapping out the mutex type requires changing a significant number
of function parameters, and templatizing the function parameter
requires the methods to be defined in the headers.
Furthermore, if LLVM is compiled with threads disabled then there
may even be no mutex to acquire anyway, so it should not be up to
individual APIs to know whether or not acquiring a mutex is required
to use those APIs to begin with. It should be up to the user of the
API.
Kevin Enderby [Tue, 17 Jun 2014 17:54:13 +0000 (17:54 +0000)]
Add "-format darwin" to llvm-size to be like darwin's size(1) -m output, and
and the -l option for the long format. Also when the object is a Mach-O
file and the format is berkeley produce output like darwin’s default size(1)
summary berkeley derived output.
Like System V format, there are also some small changes in how and where
the file names and archive member names are printed for darwin and
Mach-O.
Like the changes to llvm-nm these are the first steps in seeing if it is
possible to make llvm-size produce the same output as darwin's size(1).
Will Schmidt [Tue, 17 Jun 2014 17:04:42 +0000 (17:04 +0000)]
mark the old jit tests as unsupported for powerpc64 (for cmake)
mark the old JIT tests as unsupported for powerpc64 - CMake style.
This follows the style used for hexagon/arm64/aarch64.
The equivalent tests still run under the supported MCJIT/*
Tom Stellard [Tue, 17 Jun 2014 16:53:04 +0000 (16:53 +0000)]
R600/SI: Re-initialize the m0 register after using it for indirect addressing
We need to store a value greater than or equal to the number of LDS
bytes allocated by the shader in the m0 register in order for LDS
instructions to work correctly.
We always initialize m0 at the beginning of a shader, but this register
is also used for indirect addressing offsets, so we need to
re-initialize it any time we use indirect addressing.
Tim Northover [Tue, 17 Jun 2014 11:31:42 +0000 (11:31 +0000)]
AArch64: estimate inline asm length during branch relaxation
To make sure branches are in range, we need to do a better job of estimating
the length of an inline assembly block than "it's probably 1 instruction, who'd
write asm with more than that?".
Fortunately there's already a (highly suspect, see how many ways you can think
of to break it!) callback for this purpose, which is used by the other targets.
Evgeniy Stepanov [Tue, 17 Jun 2014 09:23:12 +0000 (09:23 +0000)]
[msan] Fix handling of multiplication by a constant with a number of trailing zeroes.
Multiplication by an integer with a number of trailing zero bits leaves
the same number of lower bits of the result initialized to zero.
This change makes MSan take this into account in the case of multiplication by
a compile-time constant.
We don't handle the general, non-constant, case because
(a) it's not going to be cheap (computation-wise);
(b) multiplication by a partially uninitialized value in user code is
a bad idea anyway.
Constant case must be handled because it appears from LLVM optimization of a
completely valid user code, as the test case in compiler-rt demonstrates.
Justin Bogner [Tue, 17 Jun 2014 06:52:47 +0000 (06:52 +0000)]
Support: Inject LLVM_VERSION_INFO into the Support library
Mimic r116632 in passing LLVM_VERSION_INFO from the Makefile build
system to the build. This improves the -version output of tools that
use llvm::cl under the configure+make system.
Jingyue Wu [Tue, 17 Jun 2014 00:42:07 +0000 (00:42 +0000)]
[InstCombine] mark ADD with nuw if no unsigned overflow
Summary:
As a starting step, we only use one simple heuristic: if the sign bits
of both a and b are zero, we can prove "add a, b" do not unsigned
overflow, and thus convert it to "add nuw a, b".
Updated all affected tests and added two new tests (@zero_sign_bit and
@zero_sign_bit2) in AddOverflow.ll
r199771 accidently broke the logic that makes sure that SROA only splits
load on byte boundaries. If such a split happens, some bits get lost
when reassembling loads of wider types, causing data corruption.
Move the width check up to reject such splits early, avoiding the
corruption. Fixes PR19250.
Juergen Ributzka [Mon, 16 Jun 2014 23:58:24 +0000 (23:58 +0000)]
[FastISel][X86] Refactor the code to get the X86 condition from a helper function. NFC.
Make use of helper functions to simplify the branch and compare instruction
selection in FastISel. Also add test cases for compare and conditonal branch.
Zachary Turner [Mon, 16 Jun 2014 22:41:08 +0000 (22:41 +0000)]
Cleanup more unreferenced MutexGuard parameters on functions.
These parameters are intended to serve as sort of a contract that
you cannot access the functions outside of a mutex. However, the
entire JIT class cannot be accessed outside of a mutex anyway, and
all methods acquire a lock as soon as they are entered. Since the
containing class already is not intended to be thread-safe, it only
serves to add code clutter.
Reed Kotler [Mon, 16 Jun 2014 22:05:47 +0000 (22:05 +0000)]
Add load/store functionality
Summary:
This patches allows non conversions like i1=i2; where both are global ints.
In addition, arithmetic and other things start to work since fast-isel will use
existing patterns for non fast-isel from tablegen files where applicable.
In addition i8, i16 will work in this limited context for assignment without the need
for sign extension (zero or signed). It does not matter how i8 or i16 are loaded (zero or sign extended)
since only the 8 or 16 relevant bits are used and clang will ask for sign extension before using them in
arithmetic. This is all made more complete in forthcoming patches.
for example:
int i, j=1, k=3;
void foo() {
i = j + k;
}
Keep in mind that this pass is not enabled right now and is an experimental pass
It can only be enabled with a hidden option to llvm of -mips-fast-isel.
Test Plan: Run test-suite, loadstore2.ll and I will run some executable tests.
Bill Schmidt [Mon, 16 Jun 2014 21:36:02 +0000 (21:36 +0000)]
[PPC64] Fix PR19893 - improve code generation for local function addresses
Rafael opened http://llvm.org/bugs/show_bug.cgi?id=19893 to track non-optimal
code generation for forming a function address that is local to the compile
unit. The existing code was treating both local and non-local functions
identically.
This patch fixes the problem by properly identifying local functions and
generating the proper addis/addi code. I also noticed that Rafael's earlier
changes to correct the surrounding code in PPCISelLowering.cpp were also
needed for fast instruction selection in PPCFastISel.cpp, so this patch
fixes that code as well.
The existing test/CodeGen/PowerPC/func-addr.ll is modified to test the new
code generation. I've added a -O0 run line to test the fast-isel code as
well.
Tested on powerpc64[le]-unknown-linux-gnu with no regressions.
Zachary Turner [Mon, 16 Jun 2014 20:54:28 +0000 (20:54 +0000)]
Clean up some unnecessary mutex guards.
These were being used as unreferenced parameters to enforce that
the methods must not be called without holding a mutex, but all
of the methods in question were internal, and the methods were
only exposed through an interface whose entire purpose was to
serialize access to these structures, so expecting the methods
to be accessed under a mutex is reasonable enough.
Louis Gerbarg [Mon, 16 Jun 2014 20:31:50 +0000 (20:31 +0000)]
Improve comments for r211040
Added comment to clarify why we r211040 choose to bail out of fast isel instead
of generating a more complicated relocation, and fix mislabelled register in the
comments of the asan test case.
Louis Gerbarg [Mon, 16 Jun 2014 17:35:40 +0000 (17:35 +0000)]
Fix illegal relocations in X86FastISel
On x86_86 the lea instruction can only use a 32 bit immediate value. When
the code is compiled statically the RIP register is not used, meaning the
immediate is all that can be used for the relocation, which is not sufficient
in the case of targets more than +/- 2GB away. This patch bails out of fast
isel in those cases and reverts to DAG which does the right thing.
Jim Grosbach [Mon, 16 Jun 2014 16:55:20 +0000 (16:55 +0000)]
LowerSwitch: track bounding range for the condition tree.
When LowerSwitch transforms a switch instruction into a tree of ifs it
is actually performing a binary search into the various case ranges, to
see if the current value falls into one cases range of values.
So, if we have a program with something like this:
switch (a) {
case 0:
do0();
break;
case 1:
do1();
break;
case 2:
do2();
break;
default:
break;
}
the code produced is something like this:
if (a < 1) {
if (a == 0) {
do0();
}
} else {
if (a < 2) {
if (a == 1) {
do1();
}
} else {
if (a == 2) {
do2();
}
}
}
This code is inefficient because the check (a == 1) to execute do1() is
not needed.
The reason is that because we already checked that (a >= 1) initially by
checking that also (a < 2) we basically already inferred that (a == 1)
without the need of an extra basic block spawned to check if actually (a
== 1).
The patch addresses this problem by keeping track of already
checked bounds in the LowerSwitch algorithm, so that when the time
arrives to produce a Leaf Block that checks the equality with the case
value / range the algorithm can decide if that block is really needed
depending on the already checked bounds .
For example, the above with "a = 1" would work like this:
the bounds start as LB: NONE , UB: NONE
as (a < 1) is emitted the bounds for the else path become LB: 1 UB:
NONE. This happens because by failing the test (a < 1) we know that the
value "a" cannot be smaller than 1 if we enter the else branch.
After the emitting the check (a < 2) the bounds in the if branch become
LB: 1 UB: 1. This is because by checking that "a" is smaller than 2 then
the upper bound becomes 2 - 1 = 1.
When it is time to emit the leaf block for "case 1:" we notice that 1
can be squeezed exactly in between the LB and UB, which means that if we
arrived to that block there is no need to emit a block that checks if (a
== 1).
projects / llvm / log