Fangrui Song [Sat, 6 Apr 2019 09:12:53 +0000 (09:12 +0000)]
[DWARF] Simplify DWARFDebugAranges::findAddress
The current lower_bound approach has to check two iterators pos and pos-1.
Changing it to upper_bound allows us to check one iterator (similar to
DWARFUnitVector::getUnitFor*).
Robert Widmann [Fri, 5 Apr 2019 21:36:50 +0000 (21:36 +0000)]
[LLVM-C] Begin to Expose A More General Binary Interface
Summary:
Provides a new type, `LLVMBinaryRef`, and a binding to `llvm::object::createBinary` for more general interoperation with binary files than `LLVMObjectFileRef`. It also provides the proper non-consuming API for input buffers and populates an out parameter for error handling if necessary - two things the previous API did not do.
In a follow-up, I'll define section and symbol iterators and begin to build upon the existing test infrastructure.
This patch is a first step towards deprecating that API and replacing it with something more robust.
Petr Hosek [Fri, 5 Apr 2019 21:30:40 +0000 (21:30 +0000)]
[gn] Support for building compiler-rt builtins
This is support for building compiler-rt builtins, The library build
should be complete for a subset of supported platforms, but not all
CMake options have been replicated in GN.
We always use the just built compiler to build all the runtimes, which
is equivalent to the CMake runtimes build. This simplifies the build
configuration because we don't need to support arbitrary host compiler
and can always assume the latest Clang. With GN's toolchain support,
this is significantly more efficient than the CMake runtimes build.
[AMDGPU] Add MachineDCE pass after RenameIndependentSubregs
Detect dead lanes can create some dead defs. Then RenameIndependentSubregs
will break a REG_SEQUENCE which may use these dead defs. At this point
a dead instruction can be removed but we do not run a DCE anymore.
MachineDCE was only running before live variable analysis. The patch
adds a mean to preserve LiveIntervals and SlotIndexes in case it works
past this.
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
[X86] Merge the different CMOV instructions for each condition code into single instructions that store the condition code as an immediate.
Summary:
Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models.
This avoids needing an isel pattern for each condition code. And it removes
translation switches for converting between CMOV instructions and condition
codes.
Now the printer, encoder and disassembler take care of converting the immediate.
We use InstAliases to handle the assembly matching. But we print using the
asm string in the instruction definition. The instruction itself is marked
IsCodeGenOnly=1 to hide it from the assembly parser.
This does complicate the scheduler models a little since we can't assign the
A and BE instructions to a separate class now.
Petr Hosek [Fri, 5 Apr 2019 19:13:54 +0000 (19:13 +0000)]
[gn] Rebase paths in symlink_or_copy against root_build_dir
We should be always rebasing paths against root_build_dir which is
the directory where scripts are run from, not root_out_dir which is
the current toolchain directory. The latter can result in invalid
paths when the action is being used from a non-default toolchain.
Current LCG doesn't check aliased functions. So if an internal function has a public alias it will not be added to CG SCC, but it is still reachable from outside through the alias.
So this patch adds aliased functions to SCC.
[PDB Docs] Add info about the hash adjustment buffer.
This necessitates adding a document describing the serialized
hash table format. This document is currently empty, although
it will be filled out in followup patches.
Use ctypes to call into SHFileOperationW with the extended NT path to allow us
to remove paths which exceed 261 characters on Windows. This functionality is
exercised by swift's test suite.
This patch changes the error message when the section specified by
--string-dump cannot be found by including the name of the section in
the error message and changing the prefix text to not imply that the
file itself was invalid. As part of this change some uses of
std::error_code have been replaced with the llvm Error class to better
encapsulate the error info (rather than passing File strings around),
and the WithColor class replaces string literal error prefixes.
Simon Pilgrim [Fri, 5 Apr 2019 14:56:21 +0000 (14:56 +0000)]
[SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCC
Second half of PR40800, this patch adds DAG undef handling to fcmp instructions to match the behavior in llvm::ConstantFoldCompareInstruction, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.).
This involves a lot of tweaking to reduced tests as bugpoint loves to reduce fcmp arguments to undef........
Don Hinton [Fri, 5 Apr 2019 13:59:24 +0000 (13:59 +0000)]
[llvm] Add isa_and_nonnull
Summary:
Add new ``isa_and_nonnull<>`` operator that works just like
the ``isa<>`` operator, except that it allows for a null pointer as an
argument (which it then returns false).
There are a variety of vector patterns that may be profitably reduced to a
scalar op when scalar ops are performed using a subset (typically, the
first lane) of the vector register file.
For x86, this is true for float/double ops and element 0 because
insert/extract is just a sub-register rename.
Other targets should likely enable the hook in a similar way.
Petar Jovanovic [Fri, 5 Apr 2019 12:58:15 +0000 (12:58 +0000)]
[TextAPI] Fix off-by-one error in the bit index extraction loop
The loop in findNextSetBit() runs one pass more than it should.
On 64-bit architectures this does not cause a problem, but 32-bit
architectures mask the shift count to 5 bits which limits the number of
shifts inside a range of 0 to 31. Shifting by 32 has the same effect as
shifting by 0, so if the first bit in the set is 1, the function will return
with Index different from EndIndexVal. Because of that, range-based for
loops iterating thorough architectures will continue until hitting a 0 in
the set, resulting in n additional iterations, where n is equal to the
number of consecutive 1 bits at the start the set.
Ultimately TBDv1.WriteFile and TBDv2.WriteFile will output additional
architectures causing a failure in the unit tests.
Pavel Labath [Fri, 5 Apr 2019 08:43:54 +0000 (08:43 +0000)]
Fix r357749 for big-endian architectures
We need to read the strings from the minidump files as little-endian,
regardless of the host byte order.
I definitely remember thinking about this case while writing the patch
(and in fact, I have implemented that for the "write" case), but somehow
I have ended up not implementing the byte swapping when reading the
data. This adds the necessary byte-swapping and should hopefully fix
test failures on big-endian bots.
Pavel Labath [Fri, 5 Apr 2019 08:26:58 +0000 (08:26 +0000)]
Fix MSVC build for r357749
MSVC found the bare "make_unique" invocation ambiguous (between std::
and llvm:: versions). Explicitly qualifying the call with llvm:: should
hopefully fix it.
Pavel Labath [Fri, 5 Apr 2019 08:06:26 +0000 (08:06 +0000)]
Minidump: Add support for reading/writing strings
Summary:
Strings in minidump files are stored as a 32-bit length field, giving
the length of the string in *bytes*, which is followed by the
appropriate number of UTF16 code units. The string is also supposed to
be null-terminated, and the null-terminator is not a part of the length
field. This patch:
- adds support for reading these strings out of the minidump file (this
implementation does not depend on proper null-termination)
- adds support for writing them to a minidump file
- using the previous two pieces implements proper (de)serialization of
the CSDVersion field of the SystemInfo stream. Previously, this was
only read/written as hex, and no attempt was made to access the
referenced string -- now this string is read and written correctly.
The changes are tested via yaml2obj|obj2yaml round-trip as well as a
unit test which checks the corner cases of the string deserialization
logic.
Piotr Sobczak [Fri, 5 Apr 2019 07:44:09 +0000 (07:44 +0000)]
[SelectionDAG] Compute known bits of CopyFromReg
Summary:
Teach SelectionDAG how to compute known bits of ISD::CopyFromReg if
the virtual reg used has one def only.
This can be particularly useful when calling isBaseWithConstantOffset()
with the ISD::CopyFromReg argument, as more optimizations may get enabled
in the result.
Also add a missing truncation on X86, found by testing of this patch.
This will introduce sign extends sometimes which might be harder to deal with than the zero we use for promoting SRL. I ran this through some of our internal benchmark lists and didn't see any major regressions.
I think there might be some DAG combine improvement opportunities in the test changes here.
Nick Lewycky [Thu, 4 Apr 2019 23:09:40 +0000 (23:09 +0000)]
An unreachable block may have a route to a reachable block, don't fast-path return that it can't.
A block reachable from the entry block can't have any route to a block that's not reachable from the entry block (if it did, that route would make it reachable from the entry block). That is the intended performance optimization for isPotentiallyReachable. For the case where we ask whether an unreachable from entry block has a route to a reachable from entry block, we can't conclude one way or the other. Fix a bug where we claimed there could be no such route.
The fix in rL357425 ironically reintroduced the very bug it was fixing but only when a DominatorTree is provided. This fixes the remaining bug.
[TextAPI] Prefix all architecture enums to fix the build on i386.
Summary: This changes the Architecture enum to use a prefix (AK_) to prevent the
preprocessor from replacing i386 with 1 when building llvm/clang for i386.
Make SourceManager::createFileID(UnownedTag, ...) take a const llvm::MemoryBuffer*
Requires making the llvm::MemoryBuffer* stored by SourceManager const,
which in turn requires making the accessors for that return const
llvm::MemoryBuffer*s and updating all call sites.
The original motivation for this was to use it and fix the TODO in
CodeGenAction.cpp's ConvertBackendLocation() by using the UnownedTag
version of createFileID, and since llvm::SourceMgr* hands out a const
llvm::MemoryBuffer* this is required. I'm not sure if fixing the TODO
this way actually works, but this seems like a good change on its own
anyways.
Appease STLs where std::atomic<void*> lacks a constexpr default ctor
MSVC 2019 casts the pointer to a pointer-sized integer, which is a
reinterpret_cast, which is invalid in a constexpr context, so I have to
remove the LLVM_REQUIRES_CONSTANT_INITIALIZATION annotation for now.
Data section relocations in wasm shared libraries are applied by the
library itself at static constructor time. This change adds a new
synthetic function that applies relocations to relevant memory locations
on startup.
Ensure that ManagedStatic is constant initialized in MSVC 2017 & 2019
Fixes PR41367.
This effectively relands r357655 with a workaround for MSVC 2017.
I tried various approaches with unions, but I ended up going with this
ifdef approach because it lets us write the proper C++11 code that we
want to write, with a separate workaround that we can delete when we
drop MSVC 2017 support.
This also adds LLVM_REQUIRE_CONSTANT_INITIALIZATION, which wraps
[[clang::require_constant_initialization]]. This actually detected a
minor issue when using clang-cl where clang wasn't able to use the
constexpr constructor in MSVC's STL, so I switched back to using the
default ctor of std::atomic<void*>.
Michal Gorny [Thu, 4 Apr 2019 14:21:38 +0000 (14:21 +0000)]
[llvm] [cmake] Add additional headers only if they exist
Modify the add_header_files_for_glob() function to only add files
that do exist, rather than all matches of the glob. This fixes CMake
error when one of the include directories (which happen to include
/usr/include) contain broken symlinks.
Lewis Revill [Thu, 4 Apr 2019 14:13:37 +0000 (14:13 +0000)]
[RISCV] Support assembling TLS add and associated modifiers
This patch adds support in the MC layer for parsing and assembling the
4-operand add instruction needed for TLS addressing. This also involves
parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers.
Jonas Paulsson [Thu, 4 Apr 2019 12:12:35 +0000 (12:12 +0000)]
[SystemZ] Bugfix in isFusableLoadOpStorePattern()
This function is responsible for checking the legality of fusing an instance
of load -> op -> store into a single operation. In the SystemZ backend the
check was incomplete and a test case emerged with a cycle in the instruction
selection DAG as a result.
Instead of using the NodeIds to determine node relationships,
hasPredecessorHelper() now is used just like in the X86 backend. This handled
the failing tests and as well gave a few additional transformations on
benchmarks.
The SystemZ isFusableLoadOpStorePattern() is now a very near copy of the X86
function, and it seems this could be made a utility function in common code
instead.
Simon Pilgrim [Thu, 4 Apr 2019 11:12:30 +0000 (11:12 +0000)]
Revert rL357655 and rL357656 from llvm/trunk:
Fix minor innaccuracy in previous comment on ManagedStaticBase
........
Make ManagedStatic constexpr constructible
Apparently it needs member initializers so that it can be constructed in
a constexpr context. I explained my investigation of this in PR41367.
........
Causes vs2017 debug llvm-tblgen to fail with "Unknown command line argument" errors - similar to the vs2019 error discussed on PR41367 without the patch....
This patch fixes .arch_extension directive parsing to handle a wider
range of architecture extension options. The existing parser was parsing
extensions as an identifier which breaks for extensions containing a
"-", such as the "tlb-rmi" extension.
The extension is now parsed as a string. This is consistent with the
extension parsing in the .arch and .cpu directive parsing.
Igor Kudrin [Thu, 4 Apr 2019 08:39:40 +0000 (08:39 +0000)]
[llvm-symbolizer] Add `--output-style` switch.
In general, llvm-symbolizer follows the output style of GNU's addr2line.
However, there are still some differences; in particular, for a requested
address, llvm-symbolizer prints line and column, while addr2line prints
only the line number.
This patch adds a new switch to select the preferred style.
[X86] Use INSERT_SUBREG rather than SUBREG_TO_REG when creating LEA64_32 during isel.
SUBREG_TO_REG is supposed to be used to assert that we know the upper bits are
zero. But that isn't the case here. We've done no analysis of the inputs.
The Fast ISel has a fallback to SelectionDAGISel in case it cannot handle the instruction.
This works as follows:
Using reverse order, try to select instruction using Fast ISel, if it cannot handle instruction it fallbacks to SelectionDAGISel
for these instructions if it is a call and continue fast instruction selections.
However if unhandled instruction is not a call or statepoint related instruction it fallbacks to SelectionDAGISel for all remaining
instructions in basic block.
However gc.result instruction is missed and as a result it is possible that gc.result is processed earlier than statepoint
causing breakage invariant the gc.results should be handled after statepoint.
Test is updated because in the current form fast-isel cannot handle ret instruction (due to i1 ret type without explicit ext)
and as a result test does not check fast-isel at all.
David L. Jones [Thu, 4 Apr 2019 02:27:57 +0000 (02:27 +0000)]
Revert r357452 - 'SimplifyCFG SinkCommonCodeFromPredecessors: Also sink function calls without used results (PR41259)'
This revision causes tests to fail under ASAN. Since the cause of the failures
is not clear (could be ASAN, could be a Clang bug, could be a bug in this
revision), the safest course of action seems to be to revert while investigating.
Sam Clegg [Thu, 4 Apr 2019 01:43:21 +0000 (01:43 +0000)]
[WebAssembly] EmscriptenEHSjLj: Don't abort if __THREW__ is defined
This allows __THREW__ to be defined in the current module, although
it is still required to be a GlobalVariable.
In emscripten we want to be able to compile the source code that
defines this symbols.
Previously we were avoid this by not running this pass when building
that compiler-rt library, but I have change out to build it using the
normal compiler path:
https://github.com/emscripten-core/emscripten/pull/8391
[XCOFF] Add functionality for parsing AIX XCOFF object file headers
Summary:
1. Add functionality for parsing AIX XCOFF object files headers.
2. Only support 32-bit AIX XCOFF object files in this patch.
3. Print out the AIX XCOFF object file header in YAML format.
[Support] On AIX, Check ENOTSUP on posix_fallocate instead of EOPNOTSUPP
Summary:
`posix_fallocate` can fail if the underlying filesystem does not support
it; and, on AIX, such a failure is reported by a return value of
`ENOTSUP`. The existing code checks only for `EOPNOTSUPP`, which may
share the same value as `ENOTSUP`, but is not required to.
[AIX] SelectionDAGNodes.h: Pack bit-fields that are meant to be packed
Summary:
Certain classes in the subject file are expected to provide different
views of a two-byte field as a collection of various bit-fields. On AIX,
the canonical layout of bit-fields would cause these classes to span
four bytes. Applying the `pack` pragma for compilers that employ the AIX
canonical layout allows these classes to fit within the expected two
bytes. In the future, the pragma would also likely need to be applied
when building with Clang on AIX.
[X86] Remove CustomInserters for RDPKRU/WRPKRU. Use some custom lowering and new ISD opcodes instead.
These inserters inserted some instructions to zero some registers and copied from virtual registers to physical registers.
This change instead inserts the zeros directly into the DAG at lowering time using new ISD opcodes
that take the extra zeroes as inputs. The zeros will then go through isel on their own to select
the MOV32r0 pseudo. Then we just need to mention the physical registers directly
in the isel patterns and the isel table and InstrEmitter will take care of inserting the necessary
copies to/from physical registers.
Summary:
Now CVType and CVSymbol are effectively type-safe wrappers around
ArrayRef<uint8_t>. Make the kind() accessor load it from the
RecordPrefix, which is the same for types and symbols.
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead.
This custom inserter existed so we could do a weird thing where we pretended that the instructions support
a full address mode instead of taking a pointer in EAX/RAX. I think was largely so we could be pointer
size agnostic in the isel pattern.
To make this work we would then put the address into an LEA into EAX/RAX in front of the instruction after
isel. But the LEA is overkill when we just have a base pointer. So we end up using the LEA as a slower MOV
instruction.
With this change we now just do custom selection during isel instead and just assign the incoming address
of the intrinsic into EAX/RAX based on its size. After the intrinsic is selected, we can let isel take
care of selecting an LEA or other operation to do any address computation needed in this basic block.
I've also split the instruction into a 32-bit mode version and a 64-bit mode version so the implicit
use is properly sized based on the pointer. Without this we get comments in the assembly output about
killing eax and defing rax or vice versa depending on whether we define the instruction to use EAX/RAX.
projects / llvm / log