David Goodwin [Mon, 10 Aug 2009 15:55:25 +0000 (15:55 +0000)]
Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
Chris Lattner [Mon, 10 Aug 2009 01:39:42 +0000 (01:39 +0000)]
Make the big switch: Change MCSectionMachO to represent a section *semantically*
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
Daniel Dunbar [Sun, 9 Aug 2009 08:19:00 +0000 (08:19 +0000)]
llvm-mc/AsmParser: Add hack to ignore Int_* and *_Int instructions for now, to
make it easier to see interesting ambiguities.
- Also, check that user doesn't try to redefine the super class. This is a wart
in the current design, in that assembler match classes aren't explicitly
declared somewhere (so there isn't a unique place to declare the super
class). This should probably be fixed.
Daniel Dunbar [Sun, 9 Aug 2009 06:05:33 +0000 (06:05 +0000)]
llvm-mc/AsmParser: Separate instruction ordering for ambiguity detection.
- We want the ordering operation to be simple, since we run it on every
match. The old ordering is also not a strict weak ordering when there are
ambiguities, which makes MSVC unhappy.
- While we are at it, detect all ambiguities instead of just the adjacent
ones. There are actually 655, for X86.
Bob Wilson [Sun, 9 Aug 2009 06:03:09 +0000 (06:03 +0000)]
Change Neon table lookup (VTBL) and table extension (VTBX) intrinsics to
take the table vectors as separate arguments, instead of the previous
approach where they were combined into one big vector.
Chris Lattner [Sat, 8 Aug 2009 23:39:42 +0000 (23:39 +0000)]
sink the 'name' and 'isdirective' state out of MCSection into its derived classes.
This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-)
Chris Lattner [Sat, 8 Aug 2009 22:41:53 +0000 (22:41 +0000)]
1. Make MCSection an abstract class.
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
Chris Lattner [Sat, 8 Aug 2009 22:38:48 +0000 (22:38 +0000)]
switch this to create coff sections for now, it doesn't really matter for
llvm-mc's purpose yet and we'll want to switch to creating semantic sections
at some point.
Add crc32 instruction and intrinsics. Add a new class of prefix
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.
Chris Lattner [Sat, 8 Aug 2009 20:43:12 +0000 (20:43 +0000)]
eliminate TargetLoweringObjectFileSparc in favor of a TAI hook.
A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.
Don't build illegal ops in DAGCombiner::SimplifyBinOpWithSameOpcodeHands().
Blackfin supports and/or/xor on i32 but not on i16. Teach
DAGCombiner::SimplifyBinOpWithSameOpcodeHands to not produce illegal nodes
after legalize ops.
Chris Lattner [Sat, 8 Aug 2009 20:22:20 +0000 (20:22 +0000)]
now that getOrCreateSection is all object-file specific,
give the impls an object-file-specific name. In the future
they can take different arguments etc.
Chris Lattner [Sat, 8 Aug 2009 20:02:57 +0000 (20:02 +0000)]
add a little function to do arbitrary string pattern matching in a
much more efficient way than a sequence of if's. Switch MatchRegisterName
to use it. It would be nice if someone could factor this out to a shared
place in tblgen :)
Use reloc_absolute_word_sext relocation for X86::MOV64(ri/mi)32 instructions,
since they are in 64 bit mode with i64immSExt32 imms. JIT is not affected since
it handles both word absolute relocations in the same way
ELF improvements:
Handle large integers, x86_fp80, ConstantAggregateZero, and two more ConstantExpr:
GetElementPtr and IntToPtr
Set SHF_MERGE bit for mergeable strings
Avoid zero initialized strings to be classified as a bss symbol
Don't allow common symbols to be classified as STB_WEAK
Add a constant to be used as a global value offset in data relocations
Remove RegisterScavenger::isSuperRegUsed(). This completely reverses the mistaken commit r77904.
Now there is no special treatment of instructions that redefine part of a
super-register. Instead, the super-register is marked with <imp-use,kill> and
<imp-def>. For instance, from LowerSubregs on ARM:
Daniel Dunbar [Sat, 8 Aug 2009 07:50:56 +0000 (07:50 +0000)]
llvm-mc/AsmMatcher: Improve match code.
- This doesn't actually improve the algorithm (its still linear), but the
generated (match) code is now fairly compact and table driven. Still need a
generic string matcher.
- The table still needs to be compressed, this is quite simple to do and should
shrink it to under 16k.
- This also simplifies and restructures the code to make the match classes more
explicit, in anticipation of resolving ambiguities.
Bob Wilson [Sat, 8 Aug 2009 06:13:25 +0000 (06:13 +0000)]
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
so I generalized the class for VTRN in the .td file to handle all 3 of them.
Bob Wilson [Sat, 8 Aug 2009 05:53:00 +0000 (05:53 +0000)]
Implement Neon VTRN instructions. For now, anyway, these are selected
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
Daniel Dunbar [Sat, 8 Aug 2009 05:24:34 +0000 (05:24 +0000)]
llvm-mc/AsmMatcher: Switch to a unified function to convert operands to MCInst,
so that terminal states are as simple as possible.
- If we were willing to assume that the order that operands get inserted in the
MCInst is fixed we could actually dispose with this altogether, although it
might be nice to have the flexibility to change it later.
Bob Wilson [Fri, 7 Aug 2009 23:53:05 +0000 (23:53 +0000)]
Add new intrinsics for Neon VTRN, VZIP and VUZP operations. Modeling these
as vector shuffles did not work out well. Shuffles that produce double-wide
vectors accurately represent the operation but make it hard to do anything
with the results. I considered splitting them up into 2 shuffles, one to
write each register separately, but there doesn't seem to be a good way to
reunite them for codegen.
Chris Lattner [Fri, 7 Aug 2009 23:13:38 +0000 (23:13 +0000)]
fix the column output stuff in the asmwriter from being dynamic and
driven by TAI to being static, driven by tblgen. This means that a
target doesn't get impacted by this stuff at all if it doesn't opt
into it.
Kevin Enderby [Fri, 7 Aug 2009 22:46:00 +0000 (22:46 +0000)]
Added Mac OS X assembler style conditional assembly. I may come back and see if
I can clean this up a bit more and do way with the TheCondState and just use
the top element on the TheCondStack if not empty. Also may tweak the code
around ParseConditionalAssemblyDirectives() to simplify the AsmParser code.
projects / llvm / log